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d a t a sh eet product speci?cation supersedes data of 2002 dec 09 2004 jan 26 integrated circuits saa6752hs mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer
2004 jan 26 2 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs contents 1 features 1.1 video input and preprocessing 1.2 video compression 1.3 audio input 1.4 audio compression 1.5 stream multiplexer 1.6 output interface 1.7 control domain 1.8 other features 2 general description 2.1 general 2.2 application fields 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 system operation 7.2 digital video input 7.3 video compression 7.4 digital audio input 7.5 audio compression 7.6 sdram interface 7.7 multiplexer 7.8 mpeg stream output port 7.9 clock generation 7.10 power control and reset 7.11 i 2 c-bus interface 7.12 exception handling 8 boundary scan test 8.1 initialization of boundary scan circuit 8.2 device identification codes 9i 2 c-bus control and status registers 10 limiting values 11 thermal characteristics 12 characteristics 13 package outline 14 soldering 14.1 introduction to soldering surface mount packages 14.2 reflow soldering 14.3 wave soldering 14.4 manual soldering 14.5 suitability of surface mount ic packages for wave and reflow soldering methods 15 data sheet status 16 definitions 17 disclaimers 18 purchase of philips i 2 c components
2004 jan 26 3 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 1 features 1.1 video input and preprocessing digital yuv input according to itu-r bt.656 (8 bits at 27 mhz) and itu-r bt.601 support of enhanced itu-r bt.656 input format containing decoded vbi data readable via i 2 c-bus; closed caption (cc), wide screen signalling (wss) and copyright information with copy generation management system (cgms) processing of non-broadcast video signals from analog vcr according to iec 756 two video clock input pins for switching two digital video sources itu-r bt.601 format conversion to 1/2d1, 2/3d1 and standard interchange format (sif) 4:2:2to4:2:0 colour format conversion decimation filtering for all format conversions adaptive median filter and motion compensated filter for input noise reduction. 1.2 video compression real-time mpeg-2 encoding compliant to main profile at main level (mp@ml) for 625 and 525 interlaced line systems supported resolutions: d1, 2/3d1, 1/2d1 and sif ipb frame, ip frame and i frame only encoding supported at all modes supported bit rates: up to 25 mbit/s i-only encoding; up to 15 mbit/s ip-only or ibp encoding. variable video bit rate mode for constant picture quality and constant bit rate mode to gain optimum picture quality from a fixed channel transfer rate access to bit rate control parameters whilst encoding to support external real-time control algorithms (e.g. constrained variable bit rate control) programmable group of pictures (gop) structure innovative motion estimation with wide search range adaptive quantization motion compensated noise filter. 1.3 audio input audio inputs: i 2 s format or eiaj format (16, 18 or 20 bits), master or slave mode at 32, 44.1 and 48 khz two digital i 2 s input ports for selection between two digital audio sources audio clock generation: 256f s or 384f s (where f s = 48 khz) locked to video frame rate (if video is present and locking is enabled) sample rate conversion to 48 khz (locked to video frame rate if enabled) for slave mode operation in all modes except digital versatile disc (dvd) compliant bypass. 1.4 audio compression dolby a (1) digital consumer encoding (ddce) also known as ac-3 (2) 2 channel audio encoding at 256 kbit/s or 384 kbit/s (only for saa6752hs/v103) mpeg-1 layer 2 audio encoding at 256 kbit/s or 384 kbit/s input data bypass for linear pulse code modulation (lpcm) and compressed audio data [mpeg-1, mpeg-2, dolby a digital (dd) and digital theatre system (dts)] according to iec 61937 preamble pc, preamble pd and bit stream information captured for identification of modes during bypass of compressed audio data for mpeg-1, mpeg-2, dd and dts according to iec 61937 audio mute via i 2 c-bus control for all modes except dvd-compliant bypass. (1) dolby is a registered trademark of dolby laboratories licensing corporation. (2) ac-3 is a registered trademark of dolby laboratories licensing corporation.
2004 jan 26 4 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 1.5 stream multiplexer multiplexing of video and audio streams according to the mpeg-2 systems standard ( iso 13818-1 ) generation and output of mpeg-2 transport streams (ts), mpeg-2 program streams (ps), packetized elementary streams (pes) and elementary streams (es) compliant to the dvd, d-vhs and dvb standards mpeg time stamp (pts/dts/scr/pcr) generation and insertion (synchronization) insertion of metadata optional generation of empty time slots for subsequent insertion of application specific data packets optional insertion of user data in the gop header and in the picture header optional automatic insertion of closed caption data according to dvd or atsc standard optional generation of transport streams with variable bit rate. 1.6 output interface parallel interface 8-bit master/slave output 3-state output port glueless interfacing with ieee 1394 chip sets (for example, pdi 1394 l11) data expansion bus interface (debi) interface. 1.7 control domain all control done via i 2 c-bus i 2 c-bus slave transceiver up to 400 kbit/s i 2 c-bus slave address select pin host interrupt flag pin. 1.8 other features single external clock or single crystal 27 mhz separate 27 mhz system clock output interface voltage 3.3 v ttl compatible digital outputs power supply voltage 3.3 and 2.5 v boundary scan test (bst) supported power-down mode single sdram system memory (16 mbit@16 bit or 64 mbit@16 bit). 2 general description 2.1 general philips semiconductors second generation real time mpeg-2 encoder, the saa6752hs, is a highly integrated single-chip audio and video encoding solution with flexible multiplexing functionality. with our expertise in two critical areas for consumer video encoding, noise filtering and motion estimation, we have pushed the boundaries for video quality even further, providing enhanced quality for low bit rates and enabling increased recording times for a given storage capacity. the saa6752hs will also enable a key driver for new consumer digital recording applications and system cost reduction. by integrating all audio encoding and multiplexing functionality we will be moving from a three chip to a one chip system, with cost efficient design and process technology, thus providing a truly low cost, high quality encoding system. the saa6752hs/v104 is intended for customers whose application does not require the ddce function. the saa6752hs gives significant advantages to customers developing digital recording applications: fast time-to-market and low development resources. by adding a simple external video input processor ic, an audio analog-to-digital converter, and an external sdram, analog video and audio sources are compressed into high quality mpeg-2 video and mpeg-1 layer 2 or ac-3 audio streams, multiplexed into a single program or transport stream for simple connection to various storage media or broadcast media. hence, making design effort for our customers a minimum, as well as removing the need for in-depth experience in mpeg encoding. low system host resources. all video and audio encoding algorithms and software are run on an internal mips a (1) processor. the saa6752hs only requires a small amount of communication from the system host processor to set up and control required encoding parameters via the i 2 c-bus. (1) mips is a registered trademark of mips technologies.
2004 jan 26 5 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 2.2 application ?elds 2.2.1 dvd based optical disc recorders (dvd+rw, dvd-rw, dvd-ram) emerging optical disc based recording systems target to replace the existing consumer recording (vcr) and playback (dvd and vcd) products. the first generation recordable dvd based products will want to maximise recording times for the 4.7 gbyte storage capacity. for these systems the saa6752hs is critical, with its superior noise filtering and motion estimation, in enabling high quality at low bit rates. playback compatibility with existing dvd decoding solutions will also be important, which is why the saa6752hs provides dolby a digital consumer (ac-3) audio encoding to allow playback through existing players implementing ddce (ac-3) decoding dominant in current dvd platforms. the dvd stream is based on mpeg program stream (ps). the saa6752hs directly outputs mpeg ps compliant to the dvd standard. 2.2.2 hdd based time shift recording hard disc drive (hdd) based time-shift systems enable personalized tv (ptv) functionality, providing consumers with new powers of control over what and when to watch broadcast content. with the audio and video content recorded digitally, identification, search and retrieval becomes a no brainer task as compared to traditional vcr functionality. combine this with electronic program guides and intelligent control, and the ptv can also analyse the viewers watching habits to search for programs likely to be of interest and automatically recorded in anticipation of the viewers preferences. since hdd recorders are closed systems, the recording format stream can be proprietary. the saa6752hs flexible multiplexing formats support a number of recording stream formats for hdd including mpeg transport stream (ts) or mpeg packetized elementary stream (pes). 2.2.3 d igital vcr (dvhs) recording a dvhs player records streams based on mpeg transport streams (ts) packed in logical tape tracks. the saa6752hs output streams are compliant with dvhs standard requirements. 2.2.4 v ideo editing / transmission / surveillance / conferencing the saa6752hs can operate as a stand-alone device in all the above applications. the saa6752hs full features and flexibility allows customers to tailor functionality and performance to specific application requirements. all required control settings such as gop size and bit rate modes can be selected via the i 2 c-bus.
2004 jan 26 6 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 3 quick reference data 4 ordering information notes 1. mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer. 2. mpeg-2 video and mpeg-audio encoder with multiplexer, but without ac-3 audio encoder. 3. saa6752hs/v103 is a replacement of saa6752hs/v101 with enhanced functionality. 4. saa6752hs/v104 is a replacement of saa6752hs/v102 with enhanced functionality. symbol parameter min. typ. max. unit v ddp digital supply voltage (pad cells) 3.0 3.3 3.6 v v ddco digital supply voltage (core) 2.3 2.5 2.7 v v dda analog supply voltage (oscillator and pll) 2.3 2.5 2.7 v i dd(tot) total analog plus digital supply current 407 453 525 ma p tot total power dissipation 0.95 1.16 1.48 w f dcxo quartz frequency (digital controlled tuning) 27 [1 - (200 10 - 6 )] 27 27 [1 + (200 10 - 6 )] mhz f sdram sdram clock frequency - 108 - mhz f scl i 2 c-bus input clock frequency 100 - 400 khz b output bit-rate 1.5 - 25 mbit/s v ih high-level digital input voltage 1.7 - 3.6 v v il low-level digital input voltage - 0.5 - +0.7 v v oh high-level digital output voltage v ddp - 0.4 - v ddp v v ol low-level digital output voltage 0 - 0.4 v t amb ambient temperature 0 - 70 c type number package name description version saa6752hs/v103 (1)(3) sqfp208 plastic shrink quad ?at package; 208 leads (lead length 1.3 mm); body 28 28 3.4 mm; high stand-off height sot316-1 saa6752hs/v104 (2)(4)
2004 jan 26 7 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5 block diagram f ull pagewidth mhc128 stream multipexer video compression reset control mips cpu gpio ram rom tap static mem debug only i 2 c-bus i 2 c-bus pi-bus host interrupt reset boundary scan sdram-interface stream domain scheduler video front-end system clock reference system clock output sdram 16 mbit @ 16-bit or 64 mbit @ 16-bit audio clock digital video input digital audio input system clock reference clock 27 mhz external clock mpeg output output interface audio compression audio interface rom ram saa6752hs fig.1 block diagram.
2004 jan 26 8 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 6 pinning symbol pin input/output (1) i max (ma) description v ssp 1 ground - pad ground sdata1 2 input - i 2 s-bus serial data input port 1 with internal pull-down resistor sclk1 3 input/output 4 i 2 s-bus serial clock port 1 with internal pull-down resistor sws1 4 input/output 4 i 2 s-bus word select port 1 with internal pull-down resistor v ddp 5 supply - pad ring supply voltage (3.3 v) sdata2 6 input/output 4 i 2 s-bus serial data port 2 with internal pull-down resistor sclk2 7 input/output 4 i 2 s-bus serial clock port 2 with internal pull-down resistor sws2 8 input/output 4 i 2 s-bus word select port 2 with internal pull-down resistor aclk 9 output 4 audio clock output (256f s or 384f s ) v ssp 10 ground - pad ground idq 11 input - reserved input with internal pull-down resistor; (recommended to connect to pin v ssp ) yuv0 12 input - video input signal bit 0 (lsb) yuv1 13 input - video input signal bit 1 yuv2 14 input - video input signal bit 2 yuv3 15 input - video input signal bit 3 yuv4 16 input - video input signal bit 4 yuv5 17 input - video input signal bit 5 yuv6 18 input - video input signal bit 6 yuv7 19 input - video input signal bit 7 (msb) v ssp 20 ground - pad ground hsync 21 input - horizontal sync input (video) with internal pull-down resistor vsync 22 input - vertical sync input (video) with internal pull-down resistor fid 23 input - video ?eld identi?cation input (odd/even ?eld) with internal pull-down resistor vclk1 24 input - video clock input 1 (27 mhz) with internal pull-down resistor v ssco 25 ground - core ground v ssco 26 ground - core ground v ddco 27 supply - core supply voltage (2.5 v) v ddco 28 supply - core supply voltage (2.5 v) v ddp 29 supply - pad ring supply voltage (3.3 v) vclk2 30 input - video clock input 2 (27 mhz) with internal pull-down resistor pdoav 31 3-state output 4 parallel stream data output for audio/video identi?er pdids 32 input - parallel stream data input for data strobe [request for packet in data expansion bus interface (debi) slave mode] with internal pull-up resistor pdosync 33 3-state output 4 parallel stream data output for packet sync v ssp 34 ground - pad ground pdoval 35 3-state output 4 parallel stream data valid output with internal pull-up resistor pdo0 36 3-state output 4 parallel stream data output bit 0 (lsb)
2004 jan 26 9 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs pdo1 37 3-state output 4 parallel stream data output bit 1 pdo2 38 3-state output 4 parallel stream data output bit 2 v ddp 39 supply - pad ring supply voltage (3.3 v) pdo3 40 3-state output 4 parallel stream data output bit 3 pdo4 41 3-state output 4 parallel stream data output bit 4 pdo5 42 3-state output 4 parallel stream data output bit 5 pdo6 43 3-state output 4 parallel stream data output bit 6 v ssp 44 ground - pad ground pdo7 45 3-state output 4 parallel stream data output bit 7 (msb) pdioclk 46 input/output 4 parallel stream clock input/output i2caddrsel 47 input - i 2 c-bus address select input with internal pull-up resistor sd_dq15 48 input/output 8 sdram data input/output bit 15 (msb) v ddp 49 supply - pad ring supply voltage (3.3 v) sd_dq0 50 input/output 8 sdram data input/output bit 0 (lsb) sd_dq14 51 input/output 8 sdram data input/output bit 14 sd_dq1 52 input/output 8 sdram data input/output bit 1 v ssp 53 ground - pad ground sd_dq13 54 input/output 8 sdram data input/output bit 13 sd_dq2 55 input/output 8 sdram data input/output bit 2 sd_dq12 56 input/output 8 sdram data input/output bit 12 v ddp 57 supply - pad ring supply voltage (3.3 v) sd_dq3 58 input/output 8 sdram data input/output bit 3 sd_dq11 59 input/output 8 sdram data input/output bit 11 sd_dq4 60 input/output 8 sdram data input/output bit 4 sd_dq10 61 input/output 8 sdram data input/output bit 10 v ssp 62 ground - pad ground sd_dq5 63 input/output 8 sdram data input/output bit 5 sd_dq9 64 input/output 8 sdram data input/output bit 9 sd_dq6 65 input/output 8 sdram data input/output bit 6 sd_dq8 66 input/output 8 sdram data input/output bit 8 v ddp 67 supply - pad ring supply voltage (3.3 v) sd_dq7 68 input/output 8 sdram data input/output bit 7 sd_dqm1 69 output 8 sdram data mask enable output bit 1 sd_dqm0 70 output 8 sdram data mask enable output bit 0 (lsb) sd_we 71 output 8 sdram write enable output (active low) v ssp 72 ground - pad ground sd_cas 73 output 8 sdram column address strobe output (active low) sd_clk 74 output 8 sdram clock output sd_ras 75 output 8 sdram row address strobe output (active low) sd_cke 76 output 8 sdram clock enable output symbol pin input/output (1) i max (ma) description
2004 jan 26 10 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs v ssco 77 ground - core ground v ssco 78 ground - core and substrate ground v ddco 79 supply - core supply voltage (2.5 v) v ddco 80 supply - core supply voltage (2.5 v) v ddp 81 supply - pad ring supply voltage (3.3 v) sd_cs 82 output 8 sdram chip select output (active low) sd_a13 83 output 8 sdram address output bit 13 (bank selection for 64 mbit) sd_a9 84 output 8 sdram address output bit 9 sd_a8 85 output 8 sdram address output bit 8 v ssp 86 ground - pad ground sd_a11 87 output 8 sdram address output bit 11 (bank selection for 16 mbit) sd_a7 88 output 8 sdram address output bit 7 sd_a12 89 output 8 sdram address output bit 12 (bank selection for 64 mbit) sd_a6 90 output 8 sdram address output bit 6 v ddp 91 supply - pad ring supply voltage (3.3 v) sd_a10 92 output 8 sdram address output bit 10 sd_a5 93 output 8 sdram address output bit 5 sd_a0 94 output 8 sdram address output bit 0 (lsb) sd_a4 95 output 8 sdram address output bit 4 v ssp 96 ground - pad ground sd_a1 97 output 8 sdram address output bit 1 sd_a3 98 output 8 sdram address output bit 3 sd_a2 99 output 8 sdram address output bit 2 sd_dqm3 100 output 8 reserved (do not connect) v ddp 101 supply - pad ring supply voltage (3.3 v) sd_dqm2 102 output 8 reserved (do not connect) sd_dq31 103 input/output 8 reserved (do not connect) sd_dq16 104 input/output 8 reserved (do not connect) v ssp 105 ground - pad ground sd_dq30 106 input/output 8 reserved (do not connect) sd_dq17 107 input/output 8 reserved (do not connect) sd_dq29 108 input/output 8 reserved (do not connect) v ddp 109 supply - pad ring supply voltage (3.3 v) sd_dq18 110 input/output 8 reserved (do not connect) sd_dq28 111 input/output 8 reserved (do not connect) sd_dq19 112 input/output 8 reserved (do not connect) sd_dq27 113 input/output 8 reserved (do not connect) v ssp 114 ground - pad ground sd_dq20 115 input/output 8 reserved (do not connect) sd_dq26 116 input/output 8 reserved (do not connect) symbol pin input/output (1) i max (ma) description
2004 jan 26 11 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs sd_dq21 117 input/output 8 reserved (do not connect) sd_dq25 118 input/output 8 reserved (do not connect) v ddp 119 supply - pad ring supply voltage (3.3 v) sd_dq22 120 input/output 8 reserved (do not connect) sd_dq24 121 input/output 8 reserved (do not connect) sd_dq23 122 input/output 8 reserved (do not connect) extclk 123 input - 27 mhz external clock input with internal pull-up resistor v ssp 124 ground - pad ground v ssa 125 ground - oscillator analog ground xtali 126 analog input - crystal oscillator input (27 mhz); note 2 xtalo 127 analog output - crystal oscillator output (27 mhz) v dda 128 supply - oscillator analog supply voltage (2.5 v) v ssco 129 ground - core ground v ssco 130 ground - core ground v ddco 131 supply - core supply voltage (2.5 v) v ddco 132 supply - core supply voltage (2.5 v) v ddp 133 supply - pad ring supply voltage (3.3 v) tdi 134 input - boundary scan test data input; pin must ?oat or set to high during normal operating; with internal pull-up resistor; note 3 tms 135 input - boundary scan test mode select; pin must ?oat or set to high during normal operating; with internal pull-up resistor; note 3 tck 136 input - boundary scan test clock; pin must be set to low during normal operating; with internal pull-up resistor; note 3 tdo 137 3-state output 4 boundary scan test data output; pin not active during normal operating; with 3-state output; note 3 v ssp 138 ground - pad ground trst 139 input - test reset input (active low), for boundary scan test (with internal pull-up resistor); notes 3 and 4 clkout 140 output 4 27 mhz system clock output test0 141 input/output 4 reserved (do not connect) test1 142 input/output 4 reserved (do not connect) v ddp 143 supply - pad ring supply voltage (3.3 v) test2 144 input/output 4 reserved (do not connect) sda 145 input/open-drain output - i 2 c-bus serial data input/output scl 146 input/open-drain output - i 2 c-bus serial clock input/output reset 147 input - reset input (active low); with internal pull-up resistor v ssp 148 ground - pad ground r ts 149 output 4 reserved (do not connect); universal asynchronous receiver/transmitter (uart) request to send output (active low) symbol pin input/output (1) i max (ma) description
2004 jan 26 12 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs cts 150 input - reserved (recommended connect to pin v ddp ); uart clear to send input; external static memory select input (active low); with internal pull-up resistor rxd 151 input - reserved (recommended connect to pin v ddp ); uart receive data; internal boot select input; with internal pull-up resistor txd 152 output 4 reserved (do not connect); uart transmit data v ddp 153 supply - pad ring supply voltage (3.3 v) sm_lb 154 input/output 4 reserved (do not connect) sm_ub 155 input/output 4 reserved (do not connect) h_irf 156 3-state output 4 host interrupt ?ag output; with internal pull-up resistor (active low) v ssp 157 ground - pad ground sm_oe 158 output 4 reserved (do not connect); static memory output enable output (active low) sm_a9 159 output 4 reserved (do not connect); static memory address output bit 9 sm_a10 160 output 4 reserved (do not connect); static memory address output bit 10 v ddp 161 supply - pad ring supply voltage (3.3 v) sm_a8 162 output 4 reserved (do not connect); static memory address output bit 8 sm_a11 163 output 4 reserved (do not connect); static memory address output bit 11 sm_a7 164 output 4 reserved (do not connect); static memory address output bit 7 sm_a12 165 output 4 reserved (do not connect); static memory address output bit 12 v ssp 166 ground - pad ground sm_a6 167 output 4 reserved (do not connect); static memory address output bit 6 sm_a13 168 output 4 reserved (do not connect); static memory address output bit 13 sm_a5 169 output 4 reserved (do not connect); static memory address output bit 5 sm_a14 170 output 4 reserved (do not connect); static memory address output bit 14 v ddp 171 supply - pad ring supply voltage (3.3 v) sm_we 172 output 4 reserved (do not connect); static memory write enable output (active low) sm_d7 173 input/output 4 reserved (do not connect); static memory data input/output bit 7 with internal pull-down resistor sm_d8 174 input/output 4 reserved (do not connect); static memory data input/output bit 8 with internal pull-down resistor sm_d6 175 input/output 4 reserved (do not connect); static memory data input/output bit 6 with internal pull-down resistor v ssp 176 ground - pad ground sm_d9 177 input/output 4 reserved (do not connect); static memory data input/output bit 9 with internal pull-down resistor sm_d5 178 input/output 4 reserved (do not connect); static memory data input/output bit 5 with internal pull-down resistor sm_d10 179 input/output 4 reserved (do not connect); static memory data input/output bit 10 with internal pull-down resistor symbol pin input/output (1) i max (ma) description
2004 jan 26 13 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs sm_d4 180 input/output 4 reserved (do not connect); static memory data input/output bit 4 with internal pull-down resistor v ssco 181 ground - internal pre-driver and substrate ground v ssco 182 ground - core ground v ddco 183 supply - core supply voltage (2.5 v) v ddco 184 supply - internal pre-driver supply voltage (2.5 v) v ddp 185 supply - pad ring supply voltage (3.3 v) sm_d11 186 input/output 4 reserved (do not connect); static memory data input/output bit 11 with internal pull-down resistor sm_d3 187 input/output 4 reserved (do not connect); static memory data input/output bit 3 with internal pull-down resistor sm_d12 188 input/output 4 reserved (do not connect); static memory data input/output bit 12 with internal pull-down resistor sm_d2 189 input/output 4 reserved (do not connect); static memory data input/output bit 2 with internal pull-down resistor v ssp 190 ground - pad ground sm_d13 191 input/output 4 reserved (do not connect); static memory data input/output bit 13 with internal pull-down resistor sm_d1 192 input/output 4 reserved (do not connect); static memory data input/output bit 1 with internal pull-down resistor sm_d14 193 input/output 4 reserved (do not connect); static memory data input/output bit 14 with internal pull-down resistor sm_d0 194 input/output 4 reserved (do not connect); static memory data input/output bit 0 (lsb) with internal pull-down resistor v ddp 195 supply - pad ring supply voltage (3.3 v) sm_d15 196 input/output 4 reserved (do not connect); static memory data input/output bit 15 (msb) with internal pull-down resistor sm_cs3 197 output 4 reserved (do not connect); static memory chip select output for external rom or ram (active low) sm_a4 198 output 4 reserved (do not connect); static memory address output bit 4 sm_a3 199 output 4 reserved (do not connect); static memory address output bit 3 v ssp 200 ground - pad ground sm_a2 201 output 4 reserved (do not connect); static memory address output bit 2 sm_a15 202 output 4 reserved (do not connect); static memory address output bit 15 sm_a1 203 output 4 reserved (do not connect); static memory address output bit 1 sm_a16 204 output 4 reserved (do not connect); static memory address output bit 16 v ddp 205 supply - pad ring supply voltage (3.3 v) sm_a0 206 output 4 reserved (do not connect); static memory address output bit 0 (lsb) sm_a17 207 output 4 reserved (do not connect); static memory address output bit 17 (msb) sm_cs0 208 output 4 reserved (do not connect) symbol pin input/output (1) i max (ma) description
2004 jan 26 14 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs notes 1. all input pins, input/output pins (in input mode), output pins (in 3-state mode) and open-drain output pins are limited to 3.3 v. 2. if used with external clock source the input voltage has to be limited to 2.5 v. 3. in accordance with the ieee 1149.1 standard. 4. special function of pin trst: a) for board designs without boundary scan implementation, pin trst must be connected to ground. b) pin trst provides easy initialization of the internal bst circuit. by applying a low level it can be used to force the internal test access port (tap) controller to the test-logic-reset state (normal operating) immediately. handbook, halfpage saa6752hs 1 208 157 53 104 52 156 105 mhc129 fig.2 pin configuration.
2004 jan 26 15 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7 functional description 7.1 system operation 7.1.1 g eneral the saa6752hs has a multi-processor architecture. the different processing and control modules are not locked to each other but run independently within the limits of the global scheduling. the data transfer between the processing units is carried out via fifo memories or the external sdram. the device is configured and the operation modes are selected via the i 2 c-bus. 7.1.2 o perating modes there are five operating modes: 1. idle. this mode is set after applying a hard reset (i.e. on power-up). in this mode the saa6752hs can be initialized by the host to the required configuration. video and audio processing is disabled. a hard reset always resets the saa6752hs configuration parameters back to the default states. 2. stop. in stop mode, the video and audio input processing is enabled but the multiplexer output remains disabled. it is possible to read status information on the input video and audio signals via the i 2 c-bus. the saa6752hs initialization settings cannot be modified, except to some specific dynamic encoding parameters (i.e. bit rate setting). 3. encode. in this mode, the multiplexer output is enabled. like stop mode, only dynamic encoding parameters can be modified in this mode. 4. paused. this mode allows the saa6752hs to make seamless transitions. restarting from paused mode will generate a stream output with sequential time stamps and mpeg buffer model content. 5. power-down. in this mode, the internal clock is disabled, sending the saa6752hs into a (non-functional) power saving state. a hard reset will re-initialize the saa6752hs. handbook, full pagewidth mhc130 power- down idle sleep hard reset hard reset stop encode paused power applied reconfigure reconfigure enable stop start start start pause fig.3 mode transition diagram.
2004 jan 26 16 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.1.3 m ode transition commands there are seven mode transition commands: 1. soft reset. like a hard reset, a soft reset can be applied in any mode, setting the saa6752hs back to idle mode and resetting all configuration parameters back to the default settings. 2. reconfigure. this command sets the saa6752hs back to idle mode without resetting the configuration parameters back to the default settings. 3. enable. this transition sets stop mode, enabling the video and audio input processing. 4. start. this transition sets encode mode, enabling the multiplexer stream output. note that if the saa6752hs is commanded to start from the idle mode, then the internal transition is via the stop mode. 5. stop. this command will disable the multiplexer stream output, setting the saa6752hs to stop mode. the current gop and/or audio frame is completed and an end of sequence bit appended to the stream. 6. pause. a pause transition will cause the multiplexer to complete the current gop and/or audio frame but no end of sequence bit is appended. the current mpeg buffer model contents are saved to provide a seamless transition on start. 7. sleep. this mode disables the internal clock. 8. forced reconfigure. a stop command whilst in the encode mode will not work in case the video or audio input signal is interrupted, because for stopping, the saa6752hs tries to finish the current gop. the forced reconfigure command allows a mode transition back to the idle state, without losing the actual configuration settings. the forced reconfiguration performs a soft reset and the automatic internal reprogramming of the i 2 c-bus registers. the forced reconfiguration will take about 200 ms; during the forced reconfiguration all register values will change to their default values before they are reprogrammed. please note that outputs, which can be switched to high-impedance or to input mode, will not be active during the forced reconfiguration. the saa6752hs is not able to process any other commands during mode transitions. in this event, a get running mode request will return a busy flag. the completion of a mode transition can also be flagged as an event using the host interrupt pin. 7.2 digital video input 7.2.1 g eneral the video front-end processes an itu-r bt.601/605 compliant video stream for conversion to 4 :2:0 format (mp@ml). it includes synchronization, digital video signal processing through several filters, subsampling, sliced/raw vbi data handling, and sdram address generation. the video interface is designed for use with philips saa7114 digital multi-standard decoder or similar video decoders. the input interface accepts a digital video input stream according to itu-r-bt.601 . 625 lines standard at 50 hz and 720 pixels by 576 lines as well as 525 lines at 60 hz and 720 pixels by 480 lines are covered. the video synchronization may either follow itu-r-bt.656 recommendation or can also be supplied by external signals (hsync, vsync and fid). the formatter module performs a colour conversion from 4 :2:2to4:2:0 format. optionally, also sif progressive downscaling and 2/3d1, 1/2d1 downscaling may be activated. the saa6752hs supports non-standard features of the saa711x series of video input processors, such as hard-wired external synchronization signals (2 and 3-wire sync), special vcr playback signal streams (iec 756 subset for vcr playback and still pictures), extraction of sliced data from the input video stream. 7.2.2 v ideo front - end configuration options the following configuration options can be selected from the host: video input port selection. two input clock pins are selectable. video input format. 525 or 625-line formats can be selected. video sync format. various combinations and polarities of hsync, vsync and field information (fid) can be selected as the source of sync signal processing. video filter settings. noise pre-filter and horizontal filters can be enabled and, if the default coefficients are not suitable for an application, new coefficients can be set. video format conversion. selection of conversion from d1 to 1/2d1, 2/3d1 or sif progressive downscaling. vbi data extraction. vbi data extraction of wss or cc data can be enabled.
2004 jan 26 17 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.2.3 v ideo encoder status information the following configuration option can be selected from the host: vbi data: wss and cc data can be read back via the i 2 c-bus. 7.2.4 d ata input format 7.2.4.1 interface de?nition the data input interface uses 13 pins, all of which are inputs (see table 1). pins yuv0 to yuv7 carry video and synchronization data and 3 pins are reserved for control purposes. two separate clock inputs allow two different signal sources to be used. the input clock can be asynchronous to the saa6752hs system clock. table 1 list of pins data input port note 1. in itu-t 656 mode sync signals are embedded in the video data input stream. the external sync signals are not used. 7.2.5 v ideo signal processing 7.2.5.1 acquisition of video data data is latched with the incoming video clock to provide robust data capture. video clock and data is unlocked to the internal system clock therefore a clock domain bridge is used. this is performed by oversampling of video clock and data with 108 mhz. 7.2.5.2 sync decoding and ?ltering to allow selection of the right portion of the video input stream, synchronization signals from the stream are recognized by a sync decoder. this checks the incoming field (fid), vertical sync and horizontal sync. it is possible to select either internal synchronization (which means that sav/eav codes in the itu 601/656 video streams are used) or externally applied hardware synchronization signals (which are given by the video input processor). in the latter case, 3 pin or 2 pin (v-sync and h-sync only) synchronization can be used. using 2 pin synchronization, the fid information is given by the timing of the transition of the v-sync. if a vertical blanking interval (vbi) starts during h-sync, the next field will be the top field, otherwise it will be the bottom field. a sync filter is used to inhibit sync signal triggering if an incorrect number of pixels or lines has been input. it also checks for the correct consecutive fields. the filter works on three different levels. an h-sync is only accepted after a predefined number of video cycles, a v-sync is only accepted after a programmed number of lines and a field is only accepted if top field follows bottom field or vice versa. 7.2.5.3 horizontal and vertical shift this function is intended for correction in synchronization of external sync signals if incorrectly timed. the amount of shift is programmable via the i 2 c-bus. 7.2.5.4 sav/eav decoder a sav/eav decoder extracts the f, v and h bits from the video timing reference code. the decoder evaluates the protection bits to be able to correct one bit errors within the code word. if multiple bit errors are detected, the protection bits are ignored and the field (f), vertical sync (v) and horizontal sync (h) bits are directly extracted from the code. 7.2.5.5 video format conversion the saa6752hs converts the input video input signal to the formats defined in table 2 controlled by the i 2 c-bus command. a 4 : 2 : 2 to 4 : 2 : 0 colour conversion is performed as this is a pre-requisite of mpeg mp@ml encoding. pin description yuv0 to yuv7 video input signal (synchronous to vclk) fid odd/even ?eld identi?cation signal; note 1 hsync horizontal synchronization signal; note 1 vsync vertical synchronization signal; note 1 vclk1 or vclk2 video clock signal (from source 1 or 2)
2004 jan 26 18 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs table 2 format conversion notes 1. the 8 pixels at the right edge of the scaled picture are not encoded. 2. top field only. 7.2.6 v ideo filtering 7.2.6.1 adaptive mean ?lter the saa6752hs uses an adaptive mean filter. there are three different filter modes that can be selected: median, averaging or no filter. the median algorithm provides better noise performance and is well suited to suppress single noise spikes without degrading the signal edges. the averaging algorithm is a standard low-pass filter so has greater impact on signal edges. the default threshold and gain coefficients of this filter can be overwritten via the i 2 c-bus to allow user optimization for different applications. 7.2.6.2 horizontal pre-?lter/decimation ?lter there is a horizontal filter for y and c and this can operate as a pre-filter or decimation filter. it is a symmetrical fir filter with up to 8 coefficients programmable via the i 2 c-bus. 7.2.6.3 vertical chrominance ?ltering for 4 :2:2to4:2:0 conversion, vertical filtering and subsampling of the chrominance is performed. the sequence of coefficients is mirrored in top and bottom field. this generates the right phases of the chrominance samples between the luminance samples (a non co-sited sampling scheme). 7.2.7 vbi data extraction the saa6752hs supports the extraction of wss and cc data using two independent vbi data extractor modules. the data is available via the i 2 c-bus. the following vbi data formats are supported: closed caption (cc525 and cc625) and wide screen signalling (wss525 and wss625). for cc525, cc625 and wss625 the sliced data from a video input processor (e.g. saa7114, saa7115 or saa7118) are extracted from the digital video input signal and can be read via the i 2 c-bus. for wss525 an internal data slicer is available which slices the oversampled raw data, which are delivered by the video input processor. the extracted wss525 signal can be read via the i 2 c-bus. optionally the automatic insertion of extracted closed caption data into the user data area of a video stream is possible (for details see section 7.3.8). 7.3 video compression 7.3.1 g eneral compression of video data is performed by the video compressor block; see fig.4. the input to this block is the uncompressed video information pre-processed by the video front-end and stored in external sdram memory. the output is a compressed video stream, compliant to mpeg-2 video elementary stream (ves) up to slice level. controlling information (for example, quantizer step size) as well as the bit stream for higher layers of the ves is generated by the embedded mips a processor of the saa6752hs. the video compressor contains several subblocks. the macroblock processor (mbp) performs generation of video es on macroblock level. controlling parameters for this task and mb headers as well as slice headers are generated by the core control subblock. bitstream formatting and concatenation of mbp bitstream and header information is done by the subblocks pre-packer and packer. mode picture format (pixel/lines) d1 720 2/3d1 480 1/2d1 352; note 1 sif 352; notes 1 and 2
2004 jan 26 19 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.3.2 v ideo encoder configuration options the following configuration options can be selected from the host: video compression settings. i, ip and ipb encoding with various gop structures can be selected. encoder bit rate. the bit rate for variable bit rate or constant bit rate modes can be programmed using bit rate and quantization control parameters. these parameters can be adjusted whilst encoding, not just set at initialization. encoder performance tuning. the ability for the user to tune encoding performance is provided by allowing control of adaptive quantization depth. also the saa6752hs allows download of new quantizer matrix contents. 7.3.3 v ideo encoder status information the following status information is available to the host: current encoder bit rate. the actual encoded bit rate, as number of bytes per gop, is available allowing the use of constrained variable bit rate algorithms to fine tune the encoding efficiency. 7.3.4 gop structure the programmable gop structure features a reference frame distance (m) up to 3, and a gop length (n) of up to 19. supported structures are real closed gop(m,n) and backward predicted closed gop(m,n). for the use of b-frames in d1 and 2/3d1 mode a 64 mbit sdram is needed. in d1 mode, b-frames will be unidirectional. backward predicted closed gops may have the first one (m = 2) or two (m = 3) b-frames referenced inside the gop dependent on the i 2 c-bus register settings. this is intended for editable applications as gops are independent of each other. non-editable gops allow the first one (m = 1) or two (m = 2) b-frames to be referenced to the p-frame in the previous gop. this is a non-editable format but has optimum encoding efficiency. this structure is sometimes called an open gop. the first one (m = 1) or two (m = 2) b-frames in the first gop of a sequence are always forced backwards predicted. table 3 gop notes 1. undefined. 2. this gop structure is defined as a real closed gop (rcg). 3. this gop structure is defined as a backward predicted closed gop (bpcg) or non-editable gop (neg), selectable via the i 2 c-bus. gop length (n) reference frame distance (m) 01 2 3 1i (1) (1) (1) 2 (1) ip (1) (1) 3 (1) ipp ibp (2) (1) 4 (1) ippp bibp (3) ibbp (2) 5 (1) ipppp ibpbp (2) (1) 6 (1) ipp...pp bibpbp (3) bbibbp (3) 7 (1) ipp...pp ibp...bp (2) ibbpbbp (2) 8 (1) ipp...pp bibp...bp (3) (1) 9 (1) ipp...pp ibp...bp (2) bbi...bbp (3) 10 (1) ipp...pp bibp...bp (3) ibbp...bbp (2) 11 (1) ipp...pp ibp...bp (2) (1) 12 (1) ipp...pp bibp...bp (3) bbi...bbp (3) 13 (1) ipp...pp ibp...bp (2) ibbp...bbp (2) 14 (1) ipp...pp bibp...bp (3) (1) 15 (1) ipp...pp ibp...bp (2) bbi...bbp (3) 16 (1) ipp...pp bibp...bp (3) ibbp...bbp (3) 17 (1) ipp...pp ibp...bp (2) (1) 18 (1) ipp...pp bibp...bp (3) bbi...bbp (3) 19 (1) ipp...pp ibp...bp (2) ibbp...bbp (2)
2004 jan 26 20 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.3.5 b it rate control the saa6752hs supports two modes of video bit rate control: variable bit rate and constant bit rate. the variable bit rate (vbr) mode is intended for burst data transfer applications, where the bit rate is allowed to vary but the image quality should be constant. in this mode, a combination of three parameters can be set: rvbr, qmin_vbr and qmax_vbr. while aiming at the target bit rate rvbr, only quantizer scale values within the range between qmin_vbr and qmax_vbr are applied. broadening this range leads to greater variations in picture quality but better adherence to rmax. constriction of this range forces a better constancy in picture quality at the expense of meeting the target bit rate. note that optimal control results require reasonable combinations of rmax, qmin_vbr and qmax_vbr. furthermore, the maximum bit rate rmax can be set. if rmax is reached in vbr mode, the cbr algorithm takes over the control by increasing the quantizer scale values temporarily (over qmax_vbr) to guarantee that rmax is never exceeded. hence, the closer rmax and rvbr are chosen, the more the control in vbr mode turns to cbr mode behaviour. the constant bit rate (cbr) mode is intended for applications, where a fixed channel rate is provided (e.g. transmission systems). a tight control of the quantizer scale is applied to make optimal use of the given bandwidth. the parameter rmax specifies the required constant bit rate. independent of the bit rate mode (cbr or vbr), a b-frame weighting factor (the weighting factor is applied to the quantization scale) can be applied to further reduce the bit rate of b-frames. in ip-only gop structures, every second p-frame is weighted by this factor generating virtual b-frames to simulate a bit rate distribution similar to ipb sequences. this feature can further improve the perceptual rate-distortion ratio by taking advantage of the inertia of the human visual system. 7.3.6 a daptive quantization adaptive quantization is an algorithm that uses internal generated statistics to fine tune the quantizer scale used for encoding a specific macroblock. for example, the controller adapts the quantization scale with respect to the local complexity distribution within a frame, resulting in a perceptually smoother picture quality. the amount of fine tuning can be adjusted by control of the adaptive quantization depth. 7.3.7 q uantizer matrix table download the mpeg standard default quantizer matrices can be overwritten to allow picture encoding optimization. 7.3.8 u ser data insertion user data insertion of up to 64 bytes is supported on gop and picture level. different modes can be selected via i 2 c-bus. 7.3.8.1 external user data insertion (permanently repeated) user data is downloaded via the i 2 c-bus to subaddresses 73h/76h and the number of inserted user data bytes is set via subaddresses 74h/75h. in encode mode the downloaded user data will be inserted permanently into the user data area of the video stream. it is possible to download a new set of user data during encode mode. the new data will be repeatedly inserted as soon as the download is finished. it is possible to stop the user data insertion with a special command. 7.3.8.2 external user data insertion (each downloaded byte inserted only once) in this mode each downloaded user data byte is inserted only once into the user data area. if no new user data is downloaded between two gop or pictures then no user data will be inserted. this mode can be used to transmit more than 64 bytes of user data from the encoder to the decoder, e.g. 1000 bytes distributed on 15 packets of 64 bytes and one packet of 40 bytes. the host has to control the insertion and repetition of user data. a host interrupt 'mode transition completed' is signalled, if not masked and the bit 9 of the exception status word is set when the user data have been read by the video encoder. then new user data can be downloaded via i 2 c-bus.
2004 jan 26 21 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.3.8.3 internal closed caption user data insertion compliant to atsc/ntsc standard automatic insertion of closed caption data into the user data 2 area on picture header level compliant to the atsc and eia-708 standard can be selected via the i 2 c-bus. closed caption data, which is delivered from the video input processor (e.g. saa7114) and captured in the video front-end will be inserted into the user data 2 area (picture header level) of the video stream. preconditions are appropriate settings of the video input processor and the vbi data extractor in the video front-end. the closed caption user data will be written for both fields. if no valid closed caption data for field 2 is available these data will be marked as invalid in the stream. at sif mode only field 1 closed captions can be inserted from the video input signal and dummy values (80h 80h) will be inserted for field 2. if extended data services (xds data, line 21 field 2) are inserted, the insertion will be transparent. no modification of the cgms-a copy information will be done. in accordance to eia-708 the closed caption data will appear in the stream in transport order. if b-frames are present the user data is re-ordered in the same way as the video frames. advanced tv closed captioning (atvcc) channel packet data (cc_type 10 or 11) is not supported, because the input signal of the encoder is an analog video signal, which can carry only ntsc closed captions, but not atv closed captions. no additional user data on picture header level can be inserted if internal closed caption user data insertion compliant to the atsc/ntsc standard is active. 7.3.8.4 internal closed caption user data insertion compliant to dvd standard automatic insertion of closed caption data into the user data area on gop header level compliant to the dvd standard can be selected via i 2 c-bus. closed caption data, which is delivered from the video input processor (e.g. saa7114) and captured in the video front-end will be inserted into the user data 1 area (gop header level) of the video stream. preconditions are appropriate settings of the video input processor and the vbi data extractor in the video front-end. the closed caption user data will be written for both fields. if no valid closed caption data for field 2 is available these data will be marked as invalid in the stream. if extended data services (xds data, line 21 field 2) are inserted, the insertion will be transparent. no modification of the cgms-a copy information will be done. the closed caption data will be inserted for each field of the gop in display order. at sif mode only field 1 closed captions can be inserted from the video input signal and dummy values (80h 80h) will be inserted for field 2. the user data is delayed by one gop period. the first gop in the stream carries dummy data marked as invalid. no additional user data on gop header level can be inserted if internal closed caption user data insertion compliant to the dvd standard is active. the amount of user data depends on the gop size: 5 bytes header and 3 bytes/field are required. with the maximum gop size of 19 this results in 5+19 2 3 = 119 bytes, which is more than the available array of 64 bytes for gop user data. therefore the 64 byte array for picture user data is also used for gop user data, if gop sizes larger than 9 are selected. then all 128 bytes, which are available for user data insertion on gop and picture header level will be used for the insertion of cc data on gop level. in this case no additional user data insertion on picture header level is possible. 7.3.9 m otion adaptive noise reduction the gain and adaptivity can be controlled to optimize encoding efficiency in case of noisy input sequences, i.e. off-air reception.
2004 jan 26 22 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.3.10 c ompression block partitioning the video compression block, shown in fig.4, contains the following sub-modules: macroblock processor (mbp). reads uncompressed video data from sdram and generates the compressed bitstream on mb level (without mb headers). addresses for frame buffer (previous frame) access are generated by the mbp. core control. performs mb and slice header generation, base address generation for the current mb (uncompressed), motion vector candidate generation, and computation of encoding statistics required by the cpu for bit rate controlling. pre-packer (part of packing unit). since the mbp output words are not necessarily fully used (i.e. some output words may contain unused bits) the pre-packer packs the output of the mbp in such a way that all words contain valid bits. this reduces the amount of memory required for storing the mb data. packer (part of packing unit). merges header and mb headers. handbook, full pagewidth mhc131 pre- packer mbp/cpm core control generic interface to/from pci-bus from video front-end to/from sdram-if to sdram-if memory packing unit video compression block packer fig.4 video compressor block diagram.
2004 jan 26 23 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.4 digital audio input 7.4.1 g eneral the audio input interface (i 2 s) accepts serial digital audio data and supports master and slave mode. the interface is able to handle 16 to 20 bits audio data with left and right channel. audio data with more than 20-bit word width is accepted as input, but the additional bits are ignored. 7.4.2 a udio port configuration options the following configuration options can be selected from the host: audio input port selection. two digital audio input ports are selectable. audio input format. various i 2 s and eiaj formats can be selected. audio input modes. master or slave mode can be selected. audio clock output. an audio clock output (256 48 khz or 384 48 khz) can be used for external analog-to-digital converter clocking. audio output. the second audio interface port can be configured as output in special applications e.g. concurrent encoding of audio and video without internal multiplexing of the two streams. 7.4.3 i nput formats the digital audio input interface can select between two digital audio input ports via i 2 c-bus control and is able to input the following audio formats: i 2 s, see fig.5 eiaj, see fig.6 eiaj alternative format. the alternative formats are defined as having the word select shifted by one clock cycle with respect to the data. eiaj and eiaj alternative format are supported for 16, 18 and 20-bit resolution. i 2 s and i 2 s alternative format are supported for 16, 18, 20 and 24-bit resolution. input data is truncated to 20 bits internally if 24-bit resolution is applied. each of the formats can be applied in master or slave mode. when in master mode, the external audio analog-to-digital convertor must be clocked using the audio clock generated by the saa6752hs. this can be set to 256 48 khz or 384 48 khz. in slave mode an internal sample rate converter converts the input sample frequency to a video frame locked 48 khz sample frequency. if video is not present and/or the clock mode is set to mode 3, the audio clock frequency is locked to the fixed nominal system frequency (crystal or external). in all other cases the audio clock will be locked to the video frame frequency.
2004 jan 26 24 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs handbook, full pagewidth mhc132 1 stereo word right data left data msb lsb msb lsb msb sws i 2 s sclk sdata fig.5 i 2 s mode format protocol. handbook, full pagewidth mhc133 1 stereo word left data right data lsb msb lsb msb lsb eiaj sws sclk sdata fig.6 eiaj mode format protocol.
2004 jan 26 25 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.4.4 a udio input processing in order to be able to cope with analog and digital sources, the i 2 s input ports can be configured as master (analog) or slave (digital). for the slave mode however, a sample rate converter will be involved, except for dvd-compliant audio bypass. table 4 reflects the different configuration possibilities. table 4 audio input processing modes notes 1. processing modes can be changed when saa6752hs is in idle mode. 2. in master mode, the external audio source must use the saa6752hs audio clock as a clock source. 3. a sample rate conversion process will convert incoming data to a nominal 48 khz audio frequency that is locked to v-sync of the video input signal (if present). the sample rate converter is not enabled for dvd-compliant bypass mode. 4. the sample rate conversion input frequency range has been selected to be compatible with class 2 spdif receivers. 5. 24-bit input option only applies to i 2 s input formats, in this event it will be truncated to 20 bits internally in the saa6752hs before processing. eiaj formats are limited to 20 bits maximum. 6. only for saa6752hs/v103. 7. in systems that use 16 mbit sdram due to system architecture constraints, lpcm bypass must be restricted to be used with i and ip video encoding only. there is no constraint if 64 mbit sdram is used. 8. the iec 60958 format defines 20 bits for an audio sample, plus 4 auxiliary bits, which can be used to extend the word length. iec 61937 uses only 16 data bits of each iec 60958 sub-frame. it depends on the settings of an external spdif to i 2 s converter if 16, 18, 20 or 24 bits are transferred to the saa6752hs. 9. for dvd-compliant bypass mode the audio clock must be locked to the video clock externally. processing mode (1) audio content format input sample frequency (khz) no. of encoded bits encoded bit rate (kbit/s) master (2) slave (3)(4) mpeg-1 l2 encoding lpcm at 16, 18, 20 or 24 bits (5) 48 32 khz 0.1% 44.1 khz 0.1% 48 khz 0.1% 20 256, 384 ddc encoding (6) lpcm at 16, 18, 20 or 24 bits (5) 48 32 khz 0.1% 44.1 khz 0.1% 48 khz 0.1% 20 256, 384 lpcm bypass (uncompressed audio format) (7) lpcm at 16, 18, 20 or 24 bits (5) 48 32 khz 0.1% 44.1 khz 0.1% 48 khz 0.1% 16 - dvd-compliant audio bypass 16 bits (8) - 48 khz (9) 16 -
2004 jan 26 26 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.5 audio compression 7.5.1 g eneral the digital audio signal from the i 2 s input port is compressed according to mpeg-1 layer 2 and ddc (ac-3) encoding (only for saa6752hs/v103). the constant bit rate is programmable via the i 2 c-bus. an audio stream with 16 to 20 bits and a sampling frequency of 48 khz can be processed. a higher accuracy of more than 20 bits is ignored. a bypass mode can be selected for lpcm for 16-bit data resolution and compressed audio signals (mpeg-1 layer 2, mpeg-2, dd and dts) according to iec 61397 or lpcm. the format of such compressed inputs is identified and made accessible via the i 2 c-bus. 7.5.2 a udio encoder configuration options the following configuration options can be selected from the host: audio processing modes. mpeg-1 l2 or ddc (ac-3) encoding (only for saa6752hs/v103) modes can be selected. two bypass modes are also available: lpcm bypass and dvd-compliant bitstream bypass. audio mute. it is possible to mute the audio data prior to encoding. 7.5.3 a udio encoder status information the following configuration options can be selected from the host: dvd-bypass header information. header information is available to allow the host to determine the content of the bypassed audio data stream. this includes information from the preamble pc, preamble pd and audio frame headers. 7.5.4 mpeg-1 layer 2 encoding mpeg-1 layer 2 encoding can be selected. the available i 2 c-bus settings are: no pre-emphasis (default setting) 50/15 m s (compliant to iso 11172-3) ccitt j.17 (compliant to iso 11172-3). 7.5.5 ddc encoding ( only for saa6752hs/v103) dolby a digital consumer (ddc) encoding mode can be selected. the encoder performance is suitable for consumer electronic recordable dvd systems. 7.5.6 lpcm bypass 16-bit lpcm audio streams can be bypassed by the audio encoder module. 7.5.7 dvd- compliant audio bypass dvd-compliant bypass and pause burst handling is selectable in accordance to iec 61937. preamble pc, preamble pd and part of the elementary stream header are captured and made available via the i 2 c-bus. if any non dvd-compliant formats are detected then these are flagged via host interrupt. table 5 dvd-compliant audio bypass mode bit rate sample frequency channel configuration mpeg-1/2 layer 2 without extension 64 to 384 kbit/s 48 khz only mono, stereo or multi-channel up to 7.1 mpeg-2 layer 2 with extension up to 912 kbit/s 48 khz only mono, stereo or multi-channel up to 7.1 dolby a digital 64 to 448 kbit/s 48 khz only 1/0, 2/0, 3/0, 2/1, 3/1, 2/2 and 3/2 dts-1 192 to 1536 kbit/s 48 khz only stereo or multi-channel up to 5.1 7.6 sdram interface 7.6.1 g eneral the external sdram is used as memory for storing video and audio information during the compression process. it is also used as a buffer for the output stream. the interfacing to and from the functional blocks is done via a number of internal fifo memories. the saa6752hs will support 16 mbit@16 bit (512k 16 2) and 64 mbit@16 bit (1024k 16 4) sdram devices. the minimum recommended speed of the sdram is 125 mhz. recommended sdrams include the samsung k4s641632d-tc/l80 and k4s161622d-tc/l80 devices.
2004 jan 26 27 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.7 multiplexer 7.7.1 g eneral the system stream multiplexer combines compressed audio and video streams into a single mpeg system stream. presentation data is synchronized by the use of time stamps as specified in the mpeg systems standards. the multiplexer ensures an mpeg-compliant multiplexing with respect to buffer maintenance, synchronization and data alignment. it takes care of the system specific requirements for d-vhs, dvd, dvb and atsc. 7.7.2 m ultiplexer configuration options the following configuration options can be selected from the host: stream format. selection of audio or video elementary stream, packetized elementary stream, program stream or transport stream options and general system parameters including maximum system bit rate, number of flushing bytes and pes header ids. transport stream system modes. in ts mode, it is possible to set packet ids and download system information tables. 7.7.3 m ultiplexer status information the following status information can be selected from the host: metabytes information. if selected and in program stream or pack stream, it is possible to insert video and audio status information into the stream output as special metabyte data packets for later system processing. number of bytes per gop. it is possible to read the current system bit rate of the output stream. 7.7.4 e lementary stream output video and audio elementary stream outputs can be selected. 7.7.5 p acketized elementary stream output packetized elementary stream (pes) outputs can be selected. there are two options: pes (dvd) and pes (ts). variable bit rate is only available in pes (dvd) mode and constant bit rate only available in pes (ts) mode. the video and audio pes ids can be programmed via the i 2 c-bus. original copy or copyright flags can also be set. 7.7.6 p rogram stream output program stream output, intended for storage recording applications, can be selected. time slot reservation for navigation packets is available. metabytes can be appended after each pack, see section 7.7.10. 7.7.7 p ack stream output a special mode called pack stream can be selected. this is a program stream but without the mpeg buffer model implemented. this minimizes the throughput time of video and audio data through the saa6752hs and is intended for applications where low latency is important. in this mode no program stream header is inserted. 7.7.8 t ransport stream output transport stream output can be selected. the video, audio and pcr (clock) packet identifiers (pids) can be programmed. system information tables can be transferred to the saa6752hs via the i 2 c-bus. if transport stream output is combined with dio master mode as output mode then packets are sent in a controlled way, so that a set-top box can be connected. 7.7.8.1 transport stream with variable bit rate optionally a transport stream without null packets, i.e. with variable bit rate can be generated. via subaddress c3h it is possible to select constant or variable ts bit rate. at constant ts bit rate mode null packets are delivered at the multiplexer output to achieve the constant ts bit rate, even if the video bit rate is variable. at variable ts bit rate mode no null packets are inserted at the multiplexer output. this mode can be used in combination with variable video bit rate. 7.7.9 i nsertion of leading null bytes for some applications it is helpful to deliver leading flushing bytes before the stream content starts. null bytes (00h) will be inserted at the beginning of a stream, if programmed by subaddress f6h. by default no null bytes will be delivered.
2004 jan 26 28 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.7.10 m etabytes data in program stream and pack stream modes, the saa6752hs can append additional metabyte data packets to the stream, providing information on sector information for downstream application processing. the video and audio metabytes format is defined in tables 6 and 7. the sector and metabytes form a block format, where each sector of 2048 bytes is followed by 16 metabytes containing data on the previous sector. table 6 video metabytes data note 1. this is the same value as used to generate the pts and dts values. byte (hex) name lsb/ msb bit description 00 identi?cation 0 to 7 55h; video 01 ?ags 0 gop start ?ag; indicates that a gop start code is present in the sector 1 gop start header; indicates that a group of gops starts in the sector 2 sequence end ?ag; indicates that a sequence end code is present in the sector 3 and 4 reserved 5 to 7 unde?ned 02 data length lsb 0 to 7 amount of non-stuf?ng bytes minus one 03 msb 0 to 7 04 time stamp lsb 0 to 7 the value of the stc at the moment that the ?rst byte of the ?rst frame arrived at the input. only 32 bits are used; note 1. 05 0 to 7 06 0 to 7 07 msb 0 to 7 08 picture start count 0 to 7 the amount of picture starts in the sector 09 picture types 0 and 1 1st picture type: 00: i picture 01: p picture 10: b picture 11: invalid type 2 reserved 4 and 5 2nd picture type: 00: i picture 01: p picture 10: b picture 11: invalid type 6 reserved 0a ?rst picture position lsb 0 to 7 position (in bytes) of the ?rst picture (or gop or sequence) start code in the sector 0b msb 0 to 7 0c second picture position lsb 0 to 7 position (in bytes) of the second picture (or gop or sequence) start code in the sector 0d msb 0 to 7 0e gop header position lsb 0 to 7 position (in bytes) of the gop start code in the sector, if present, else 0000 0f msb 0 to 7
2004 jan 26 29 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs table 7 audio metabytes data note 1. this is the same value as used to generate the pts value. byte (hex) name lsb/ msb bit description 00 identi?cation 0 to 7 aah; audio 01 ?ags 0 reserved 1 terminated audio ?ag; this ?ag is only set at the end of a recording session and indicates that this sector is not completely ?lled with audio data 2 synchronization ?ag; indicates that the audio data in the sector is related in time to the beginning of a video object unit (vobu) 3 reserved 4 reserved 5 to 7 audio pack type: 000: mpeg-1 layer 2 or mpeg-2 without extension 010: mpeg-2 with extension 011: ddce 100: dts-1 (512 samples/frame) 101: reserved 110: reserved 111: lpcm 16-bit stereo 48 khz 02 data length lsb 0 to 7 amount of non-stuf?ng bytes minus one 03 msb 0 to 7 04 time stamp lsb 0 to 7 the value of the stc at the moment that the ?rst byte of the ?rst frame arrived at the input. only 32 bits are used; note 1. 05 0 to 7 06 0 to 7 07 msb 0 to 7 08 reserved 0 to 7 00 09 frame start count 0 to 7 the amount of frame starts in the sector 0a ?rst frame position lsb 0 to 7 position (in bytes) of the ?rst frame in the sector 0b msb 0 to 7 0c last frame position lsb 0 to 7 position (in bytes) of the last frame in the sector 0d msb 0 to 7 0e reserved 0 to 7 00 0f reserved 0 to 7 00
2004 jan 26 30 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.8 mpeg stream output port 7.8.1 g eneral the mpeg stream output port connects the saa6752hs multiplexer output to the outside world. the parallel interface performs a parallel output transition of audio and video data to an externally connected device and supports 3-bus protocol modes. 7.8.2 o utput port configuration options the following configuration options can be selected from the host: output protocol. three output protocols can be selected: dio slave mode, dio master mode and debi slave mode and associated signalling pin polarities. output disable. output can be set to high-impedance if the saa6752hs is not used in application. 7.8.3 d ata output format the data to be transmitted have a width of 8 bits in all modes. the data output port supports dio and debi bus protocols. the bus protocol mode is set via an i 2 c-bus controlled register. the debi protocol provides only a transmission of 8-bit data block transfer without address decoding. 7.8.4 p rotocol description table 8 output port de?nitions 7.8.4.1 dio master mode the pdioclk clock for the dio interface is derived from the system clock by a division of the 27 mhz clock by 3 or by 4, generating a data output clocked at 9 or 6.75 mhz. a pdoval signal indicates whether current data at the output is valid. if the output buffer is empty the pdoval signal will stay low. the number of valid pulses indicate the real number of data transmissions. the signal pdosync in conjunction with pdoval indicates the first byte of a transport stream packet. port i/o description pdids i request from external system if interface is in debi slave mode. pdioclk i/o output clock to the external system if interface is set to dio master mode. input clock to the saa6752hs if interface is set to dio slave mode. pdo[7:0] o output data (8-bit parallel) pdosync o indicates a ?rst byte of a data packet (for transport streams in dio mode). pdoav o indicates when an audio packet is output (for transport stream). pdoval o indicates whether currently sent data is valid. handbook, full pagewidth mhc134 output interface saa6752hs data receiver pdioclk pdosync pdoav pdo [ 7:0 ] pdoval data clock dsync audio/video qualifier valid n.c. pdids fig.7 dio master mode protocol.
2004 jan 26 31 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs handbook, full pagewidth mhc135 00 01 ba pdioclk pdo [ 7:0 ] pdoval fig.8 data transfer in dio master mode. handbook, full pagewidth mhc136 pdioclk pdo [ 7:0 ] pdosync pdoval 188 bytes fig.9 dio master mode, transport stream packet.
2004 jan 26 32 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.8.4.2 dio slave mode the saa6752hs can be enabled in a dio slave mode where the data receiver acts as master. pdo, pdosync and pdoav are clocked out by the internal clock; earliest two internal clock cycles e.g. 36 to 58 ns after the falling edge of the external clock. the external clock pdioclk should not exceed a maximum of 9 mhz. the pdoval signal still indicates if data is available in the output buffer. to operate in this mode, the pdids request input must be set to logic 1. handbook, full pagewidth mhc137 output interface saa6752hs data receiver pdioclk pdosync pdoav pdo [ 7:0 ] pdoval data clock dsync audio/video qualifier valid '1' pdids fig.10 dio slave mode protocol. handbook, full pagewidth mhc138 10 00 01 ba pdioclk pdo [ 7:0 ] pdoval fig.11 data transfer in dio slave mode.
2004 jan 26 33 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.8.4.3 debi slave mode the saa6752hs supports debi slave mode with a block transfer of 8-bit data. this can be used for interfacing with a pci bridge (for example, an saa7146a chip set). there is no addressing phase necessary. the transfer starts with recognition of a pdids pulse. the requested data, pdo[7:0], is transferred when the pdoval signal goes active, indicating that data is available in the output buffer. in the event of interfacing to an saa7146a chip set, the pdoval pin is connected to the dtack_rdy pin and serves as a handshake. the lds_rdn and uds_wrn signals should be used to generate the pdids signal. note that to operate correctly to the debi transfer protocol the valid output signal should be programmed negative by i 2 c-bus command and a 3.3 k w resistor to v ddp is recommended. handbook, full pagewidth mhc139 output interface saa6752hs data receiver (saa7146a) pdioclk n.c. n.c. n.c. pdosync pdoav pdo [ 7:0 ] pdoval ad16in dtack_rdy lds_rdn uds_wrn pdids fig.12 debi slave mode protocol. handbook, full pagewidth mhc140 xx 01 xx 02 pdo [ 7:0 ] pdoval pdids fig.13 data transfer in debi slave mode.
2004 jan 26 34 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.9 clock generation 7.9.1 g eneral the saa6752hs is designed to operate with a single fundamental 27 mhz crystal or an external 27 mhz clock. from these clock sources an internal pll produces the 27 mhz, 54 mhz and 108 mhz frequencies needed for operation. it is possible to use a third overtone crystal in combination with a 9 mhz external trap. in this event clock mode 2 and tuning by the i 2 c-bus commands are not usable. 7.9.2 c lock configuration options the following configuration options can be selected from the host: clock mode. dependent on the type of application (i.e. video frame locked, reference clock locked etc.), three different clock modes are available clock source. the clock can be generated from an internal crystal controlled clock or an external source. if from a crystal then a fine tune adjustment is available clock output. it is possible to enable a system clock output so that the 27 mhz clock can be used elsewhere by the user. 7.9.3 c lock m odes the saa6752hs internal pll can be configured in three different clock modes: clock modes 1, 2 and 3. a definition of the clock modes is shown in table 9. the clock modes are intended for different applications: clock mode 1. system clock reference locked to input video frame frequency. intended for applications where the output stream is recorded directly onto a medium (i.e. dvd video recorder). clock mode 2. crystal locked to input video frame frequency. intended for applications that require both recording and direct playback. however it is limited by the required accuracy of the input video frame frequency clock mode 3. crystal free-running. intended for applications where the output stream is played real time directly by a decoder. to meet the requirements for each clock mode the conditions specified in table 10 must be met. table 9 clock modes note 1. the stream contents are mpeg-compliant but the time stamps are not synchronized with real time (i.e. dependent on the accuracy of the video input frame frequency). playback of such a stream is mpeg-compliant due to the re-generation of time synchronization. table 10 clock modes requirements note 1. the nominal video frame frequency is dependent on the video mode set: 525 or 625 lines. clock mode output stream time-stamp compliance system frequency system clock reference frequency 1 dvd-compliant (1) crystal frequency 27 mhz video frame frequency accuracy 2 dvd and mpeg-compliant 27 mhz video frame frequency accuracy 27 mhz video frame frequency accuracy 3 mpeg-compliant crystal frequency crystal frequency clock mode crystal frequency external clock frequency input video frame frequency (1) 1 27 mhz 0.1% 27 mhz 0.1% nominal - 8% to nominal + 2% 227 (1 200 10 - 6 ) mhz (to allow ?ne tuning via pll) not applicable nominal (1 200 10 - 6 ) 327 (1 30 10 - 6 ) mhz 27 (1 30 10 - 6 ) mhz not applicable
2004 jan 26 35 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 7.9.4 c lock mode 2 auto - switch an auto-switch mode is available if clock mode 2 is selected. in this event the pll will switch to clock mode 1 or 3 if the conditions for clock mode 2 are no longer met (i.e. video frame frequency outside the range 1 200 10 - 6 ). the auto-switch preference is set by an i 2 c-bus command during the saa6752hs initialization. if auto-switch occurs then a host interrupt can be flagged. 7.9.5 c rystal tuning it is possible to tune the crystal frequency by up to 1 200 10 - 6 via the i 2 c-bus. if necessary this can be used to achieve the mpeg-2 accuracy of 1 20 10 - 6 with standard crystals. 7.9.6 e xternal clock source it is possible to use an external system clock. for start-up before switching to the external clock input a crystal has to be connected or the external frequency has to be applied to pin xtali. the input voltage for this pin must be limited to 2.5 v. an external clock source cannot be used with clock mode 2. 7.9.7 a udio clock a switchable sampling frequency for an audio analog-to-digital converter (adc) is generated by the internal pll. two sampling frequencies are selectable: 256 48 khz and 384 48 khz. this clock output can be used as clock signal for an external audio adc. the system clock reference frequency as described in table 9, is used as reference for the internal pll generating the audio clock. 7.10 power control and reset 7.10.1 g eneral an external reset pulse at power-up is needed to start-up the saa6752hs. this will start the oscillator and initialize hardware and firmware. the saa6752hs can be set to a power saving sleep mode where all internal clocks are switched off. in this mode restarting can only be done by a hard reset pulse. 7.11 i 2 c-bus interface 7.11.1 g eneral the i 2 c-bus interface within the saa6752hs is a slave transceiver. it is used for all control settings. the read mode may be used to read back error or status codes. the i 2 c-bus interface is compliant to the i 2 c-bus standard at 100 khz and 400 khz clock frequency and suitable for bus line voltage levels of 3.3 v. if an i 2 c-bus with higher voltage is used by an application, it is possible to add a small interface between 3.3 v and a higher voltage level. only two mosfet transistors (e.g. bsn10, bsn20 or bss83) are needed. a description of this circuit is available at http://www.semiconductors.philips.com/i2c/facts/ information about the i 2 c-bus can be found in the brochure the i 2 c-bus and how to use it (order number 9398 393 40011). 7.11.2 s lave a ddresses two write i 2 c-bus slave addresses (sad) are available, 40h and 42h (8-bit), dependent on the state of address select pin i2caddrsel. this avoids possible address conflict of addresses with other devices. a high-level at the address selection pin will set the device write address to 42h. similarly for read operations there are two slave addresses: 41h and 43h. a high-level at the address selection pin will set the device read address to 43h. 7.12 exception handling 7.12.1 g eneral the saa6752hs is capable of flagging certain events to a host via a host interrupt flag pin h_irf. the host is able to read back a 16-bit status word via the i 2 c-bus to identify the specific event and take action accordingly. detectable events include copyright violations, loss of input synchronization, dvd compliance errors etc. 7.12.2 e xception conditions a list of the saa6752hs exception conditions, as indicated by the status word, is defined in table 11. the i 2 c-bus subaddress is 12h (see table 14).
2004 jan 26 36 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs table 11 interrupt status de?nition status word bit exception condition response if exception is detected 0 video copyright violation saa6752hs continues encoding; note 1. 1 input video signal not detected or lost saa6752hs continues encoding but outputs audio es packets only; saa6752hs will resynchronize if video input is recommenced; notes 2 to 4. 2 when a difference between the v-sync period in i 2 c-bus settings and in the video input signal is detected saa6752hs continues but frames may be lost during the event. 3 clock mode 2 out of range if enabled, the saa6752hs pll will auto-switch to clock mode 1 or 3 as programmed. 4 output buffer over?ow (due to loss of data read command) stream output stops or corrupted data will be delivered; reset or forced recon?gure needed to recover. 5 video and audio frames out of alignment ratio between number of generated audio frames and number of generated video frames is not nominal; time stamps remain correct; note 5. 6 input audio not dvd-compliant (to iec 61937) saa6752hs continues encoding but will not include audio packets. incorrect preamble pc sampling frequency out of range bit rate out of range 7 audio format change detected in dvd bypass mode saa6752hs continues encoding but will not include audio packets. 8 audio pause burst detected saa6752hs continues operation. 9 saa6752hs mode transition complete; desired operation mode has been reached saa6752hs continues operation. if external user data insertion in mode only once is active: insertion of user data has been finished and the host can send new user data 10 illegal i 2 c-bus command saa6752hs ignores the i 2 c-bus command. i 2 c-bus command not recognized command in invalid mode command parameter error 11 general error saa6752hs will go to idle mode if time-out is enabled or stop operating if time-out is disabled; in case of the later a forced recon?gure is recommended. 12 input audio word select signal not detected or audio stream stopped after exception status bit 4, 6, 7 or 8 saa6752hs continues encoding but outputs video es packets only; transition to stop needed to recover.
2004 jan 26 37 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs notes 1. no copy flag is only detected if the correct wss vbi mode is enabled. 2. this error flag detects mismatches between the input video format (525 or 625) and saa6752hs video setting (525 or 625). video syncs out of range are also detected. 3. a loss of video sync is flagged if 10 consecutive syncs are not detected. 4. for stream types which include video mode transitions to encode or idle/stop will not be finished, if no video is present. a pending mode transition can be stopped by forced reconfigure. 5. in clock mode 1 and 3 this can occur due to discontinuity in the video input signal. in applications, which require an exact ratio between the number of generated audio frames and the number of generated video frames, the host might start a corrective action. in clock mode 3 this exception can be ignored; it will happen after some encoding time, because the audio processing is locked to the system frequency and video processing depends on the video input frequency. 13 vbi wss data has been captured saa6752hs continues operation. 14 vbi cc data has been captured saa6752hs continues operation. 15 memory manager resynchronization occurred after discontinuity in the video input signal saa6752hs continues operation, but a forced recon?gure is recommended. status word bit exception condition response if exception is detected 7.12.3 h ost interrupt operation a low level as signalled by the host interface pin indicates that an exception condition has been detected. the host interrupt flag pin h_irf is reset to high by reading the interrupt status word via the i 2 c-bus. 7.12.4 i nterrupt masking it is possible to mask any combination of exception conditions by setting a 16-bit interrupt mask via the i 2 c-bus. 8 boundary scan test the saa6752hs has built-in logic and 5 dedicated pins to support boundary scan testing, which allows board testing without special hardware (nails). the saa6752hs follows the ieee std. 1149.1 - standard test access port and boundary scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are: test mode select (tms), test clock (tck), test reset ( trst), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, sample, clamp and idcode are all supported (see table 12). details on the jtag bst-test can be found in the specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) description of the saa6752hs is available on request. 8.1 initialization of boundary scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset), when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting pin trst to low. 8.2 device identi?cation codes a device identification register is specified in ieee std. 1149.1b-1994 . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and determination of the version number of ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between tdi and tdo of the ic.
2004 jan 26 38 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs the identification register will load a component specific code during the capture_data_register state of the tap controller and this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo); see fig.14. table 12 bst instructions supported by the saa6752hs inst description bypass this mandatory instruction provides a minimum length serial path (1-bit) between tdi and tdo, when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing, when not all ics have bst. it addresses the bypass register, while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. handbook, full pagewidth mhc141 xxxx 0010 1011 0110 0110 0000 0010 101 4-bit version code 16-bit part number e m s 11-bit manufacturer identification 1 31 msb lsb 28 27 12 10 tdo 11 tdi fig.14 32 bits of identification code.
2004 jan 26 39 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 9i 2 c-bus control and status registers tables 13 to 26 list the i 2 c-bus instructions intended for functional control and status. column m identifies the saa6752hs modes that are valid for each i 2 c-bus instruction. the key is: i - write and/or read valid in idle mode p- write and/or read valid in paused mode s - write and/or read valid in stop mode e - write and/or read valid in encode mode all - write and/or read valid in idle, encode, paused and stop mode. table 13 i 2 c-bus control note 1. paused mode transitions are not applicable to transport stream and dio output mode combination, only transport stream and deb i output mode combination. adr hex m command name r/w size/position parameter/range default description 00 all soft reset w none none - this command resets the saa6752hs to its default settings. 01 i enable w none none - go to stop mode from idle mode 02 i, p, s start w none none - go to encode mode 03 e stop w none none - go to stop mode from encode mode 04 e pause (1) w none none - go to paused mode from encode mode 05 e, p, s recon?gure w none none - go to idle mode 06 i sleep w none none - go to power-down mode 07 e, p, s forced recon?gure w none none - go to idle mode without completing the current gop/audio frame. this is intended for use in cases similar to no video/audio input present. 08 i enable system time-out r/w 1 byte disabled enables saa6752hs to time-out to idle mode if stop to idle transition cannot be completed (i.e. due to no video signal being present). if a general error event is detected, the saa6752hs will automatically switch to idle mode via forced recon?gure. bit 0 = 1 enabled bit 0 = 0 disabled
2004 jan 26 40 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 14 i 2 c-bus status table 15 i 2 c-bus sdram size adr hex m command name r/w size/position parameter/range default description 10 all get running mode r 1 byte - this command gets the actual running mode from the saa6752hs and is read-only. the busy ?ag indicates that the saa6752hs is working at a control command. if the busy ?ag is set, the saa6752hs skips all received i 2 c-bus commands. bit 0 = 1 idle bit 1 = 1 encoding bit 2 = 1 stopped bit 3 = 1 paused bit 4 = 1 reserved bit 5 = 1 busy ?ag 11 all status mask w 2 bytes (16 bits) all 0s masking of events; see table 11 bit = 0 event disabled bit = 1 event enabled 12 all interrupt status r 2 bytes (16 bits) - this command allows reading a status register. reading the status will clear the status and reset the interrupt assertion pin. bit = 0 no event detected bit = 1 event detected 13 all get version number r 12 bytes -- this command allows reading of the current mips a ?rmware version number, hardware number and the audio dsp ?rmware number. each number contains 4 bytes. adr hex m command name r/w size/position parameter/range default description 20 i bus width and memory size r/w 1 byte 16 bit 64 mbit bus width of the sdram interface and size of connected sdram bit[1:0] = 00 16 mbit 16-bit wide bit[1:0] = 10 64 mbit 16-bit wide bit[1:0] = 11 reserved
2004 jan 26 41 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 16 i 2 c-bus clock static/dynamic settings adr hex m command name r/w size/position parameter/range default description 30 i clock mode r/w 1 byte mode 1 bit[1:0] = 01 mode 1 mode 1: crystal frequency ?xed; scr frequency frame locked to v-sync bit[1:0] = 10 mode 2 mode 2: crystal frequency frame locked to v-sync bit[1:0] = 11 mode 3 mode 3: crystal frequency ?xed 31 i clock source r/w 1 byte crystal clock this command is used to switch from an internal crystal controlled clock source to an external clock source and vice versa. bit0=0 cr ystal clock bit1=1 e xternal clock 32 i clock auto mode r/w 1 byte mode ?xed this command sets the behaviour of the saa6752hs in clock mode 2 if video sync cannot be achieved. either mode 2 is continued or the saa6752hs will automatically switch to mode 1 or mode 3, as selected. bit[1:0] = 00 mode ?xed bit[1:0] = 01 enable mode 2 and 1 auto-switch bit[1:0] = 10 enable mode 2 and 3 auto-switch 33 i enable system clock output r/w 1 byte disable this command outputs the internal crystal generated clock (27 mhz) to an output pin clkout for use in other parts of an application. bit0=0 disabled bit0=1 enabled 34 all adjust crystal oscillator r/w 1 byte - 128 to +127 0 adjust the frequency of the oscillator
2004 jan 26 42 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 17 i 2 c-bus video front-end input interface static settings adr hex m command name r/w size/position parameter/range default description 40 i 625/525 r/w 1 byte 625 de?nes the input signal either as 625 lines or 525 lines bit[1:0] = 00 625 bit[1:0] = 01 525 41 i subsampling type r/w 1 byte d1 speci?es the subsampling type; remark: if the subsampling type is changed, then the horizontal shift (address 45h) will be overwritten with the default values and the horizontal ?lter (addresses 53h, 54h and 55h) will be initialized with appropriate parameter bit[1:0] = 00 d1 bit[1:0] = 01 2 / 3 d1 bit[1:0] = 10 1 / 2 d1 bit[1:0] = 11 sif 42 i video sync format r/w 1 byte 0 de?nes the incoming video sync sources bit[1:0] = 00 h-sync, v-sync and field identi?cation (fid) information coded in the eav/sav bytes complying to itu-r bt.656 bit[1:0] = 01 separate h-sync, v-sync and fid signals input to from external source(s) bit[1:0] = 10 separate h-sync and v-sync signals input to from external source(s) 43 i video clock select r/w 1 byte video clock 1 de?nes which external video input clock is used bit 0 = 0 video clock 1 bit 0 = 1 video clock 2 44 i vertical sync timing adjustment r/w 2 bytes 0, 0 remark: if a vertical sync timing adjustment different from 0 is used, then a horizontal shift of minimum 2 pixels must be programmed in subaddress 45h. byte 0 0 to 225 de?nes the number of shifted lines in the top ?eld byte 1 0 to 225 de?nes the number of shifted lines in the bottom ?eld
2004 jan 26 43 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 45 i horizontal shift r/w 2 bytes 0 to 511 (bits 0 to 8) 0 (d1, 2 / 3 d1) or 8( 1 / 2 d1, sif) de?nes the number of shifted cycles for every line; remark: 4 cycles correspond to 2 pixels; only multiple of 4 should be programmed 46 i sync polarity r/w byte 000 de?nes the polarity of the sync signals bit 0 = 0 h-sync signal high for horizontal blanking bit 0 = 1 h-sync signal low for horizontal blanking bit 1 = 0 v-sync signal high for vertical sync bit 1 = 1 v-sync signal low for vertical sync bit 2 = 0 fid signal low for ?rst ?eld bit 2 = 1 fid signal high for ?rst ?eld 47 i disable forced ?eld toggle r/w bit 0 = 0 enable forced ?eld toggle 0 if no fid polarity transitions are detected in the input signal, then an internal toggle of fid polarity ensures the encoding of some frames. bit 0 = 1 disable forced ?eld toggle if no fid polarity transitions are detected in the input signal, then no frames are encoded. adr hex m command name r/w size/position parameter/range default description
2004 jan 26 44 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 18 i 2 c-bus video front-end ?lters static/dynamic settings adr hex m command name r/w size/position parameter/range default description 50 i, e, p, s noise pre-?lter off/on r/w 1 byte off enables or disables noise pre-?lter and selects the mode for this ?lter bit[1:0] = 00 off bit[1:0] = 01 median ?lter bit[1:0] = 10 average ?lter 51 i, e, p, s noise pre-?lter coef?cients r/w 4 bytes 4 6 bits; bits 0 to 5 valid 33h, 20h, 16h, 0dh de?nes the ?lter coef?cients for the noise pre-?lter 52 i, e, p, s noise pre-?lter thresholds r/w 3 bytes 3 6 bits; bits 0 to 5 valid 10, 15, 20 de?nes the threshold coef?cients for the median ?lter 53 i, e, p, s horizontal ?lter off/on r/w 1 byte off enables or disables the horizontal ?lter by bypassing bit 0 = 0 off bit0=1 on 54 i, e, p, s horizontal ?lter coef?cients r/w 16 bytes array of word (8 10 bits) ?rst word = 256, the others = 0 de?nes the coef?cients for the horizontal ?lter; the default applies to d1 mode only. when other subsampling modes are selected the saa6752hs automatically overwrites the horizontal ?lter coef?cients with the appropriate parameters. 55 i, e, p, s horizontal ?lter scaling factor r/w 1 byte (4 bits) 0 to 15 8 de?nes the scaling factor for the horizontal ?lter; the default applies to d1 mode only. when other subsampling modes are selected the saa6752hs automatically overwrites the horizontal ?lter scaling parameter with the appropriate parameter.
2004 jan 26 45 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 19 i 2 c-bus video front-end vbi data extraction adr hex m command name r/w size/position parameter/range default description 60 i vbi mode select w 5 bytes - bit 0 = 0 wss mode selects between wss and cc modes bit 0 = 1 cc mode bit 8 = 0 data input sliced selects if the input data is sliced by the video input processor (sliced) or by the saa6752hs (unsliced). bit 8 = 1 data input unsliced sliced data sent in case of sliced input data bit[17:16] data type[3:2] the data type compared with the data type ?eld in the vbi data header for extraction decision; bits 3 and 2. bit[23:18] sdid, 0 to 63 the sdid compared with the sdid ?eld in the vbi data header for extraction decision. bit[28:24] line number, 0 to 31 line number of data as set by the video input processor bit 29 = 0 top field ?eld dependent on video input processor setting bit 29 = 1 bottom field bit[31:30] data type[1:0] the data type compared with the data type ?eld in the vbi data header for extraction decision; bits 1 and 0. bit 32 = 1 field qualifier mask sdid match the sdid bit 33 = 1 field qualifier mask data type match data type bit 34 = 1 field qualifier mask field match ?eld bit 35 = 1 field qualifier mask line number match line number bit[39:36] reserved must be set to zero
2004 jan 26 46 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 60 i vbi mode select (continued) w continued unsliced data - sent in case of unsliced input data bit[20:16] line number for bottom, 0to31 line number for bottom ?eld as set by the video input bit[28:24] line number for top, 0to31 line number for top ?eld as set by the video input bit[37:32] reserved must be set to zero bit 38 = 1 field qualifier mask line field 1 match if ?eld = top and line = line number bit 39 = 1 field qualifier mask line field 2 match if ?eld = bottom and line = line number 61 i wss data enable r/w 1 byte disabled enables or disables wss data extraction bit[1:0] = 00 disabled bit[1:0] = 01 enabled bit[1:0] = 10 enabled without checksum 62 all wss read data r 2 bytes -- wss data and ?ag indicating valid data bit[13:0] wss data bit 15 = 0 valid data bit 15 = 1 invalid or previous data 63 i cc data enable r/w 1 byte disabled enables the closed caption data extraction bit 0 = 0 disabled bit 0 = 1 enabled 64 all cc read data r 3 bytes - cc data and ?ags indicating valid data and current ?eld bit[15:0] cc data bit 16 = 0 top ?eld bit 16 = 1 bottom ?eld bit 23 = 0 valid data bit 23 = 1 invalid data adr hex m command name r/w size/position parameter/range default description
2004 jan 26 47 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 65 i user data insertion mode r/w 1 byte 00h selects the user data insertion mode bit 0 = 0 always repeated external user data insertion into gop header (user data 1) bit 0 = 1 only once bit 1 = 0 always repeated external user data insertion into picture header (user data 2) bit 1 = 1 only once bit 2 = 0 disabled internal user data insertion of closed caption data into gop header user data area according to dvd standard. remark: only one internal user data insertion mode can be active at the same time, either bi t2=1 or bit3=1. bit 2 = 1 enabled bit 3 = 0 disabled internal user data insertion of closed caption data into picture header user data area according to atsc/ntsc standard. remark: only one internal user data insertion mode can be active at the same time, either bi t2=1 or bit3=1. bit 3 = 1 enabled bit4=0 - stop user data insertion into gop header user data area. this bit can be used in all operation modes. setting this bit to logic 1 (= stop) deletes the downloaded gop user data and resets bit 2 to disabled. bit 4 = 1 stop bit5=0 - stop user data insertion into picture header user data area. this bit can be used in all operation modes. setting this bit to logic 1 (= stop) deletes the downloaded picture user data and resets bit 3 to disabled. bit 5 = 1 stop bit 6 reserved must be set to zero bit 7 reserved must be set to zero adr hex m command name r/w size/position parameter/range default description
2004 jan 26 48 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 20 i 2 c-bus video encoder: general adr hex m command name r/w size/position parameter/range default description 70 i disable video encoder r/w 1 byte enabled speci?es if the video encoder is enabled. if the video encoder is disabled, no video data will be inserted in the output stream. bit 0 = 0 enabled bit 0 = 1 disabled 71 i bit rate mode r/w 1 byte vbr de?nes the encoding bit rate control mode (variable or constant bit rate) bit 0 = 0 vbr bit 0 = 1 cbr 72 i gop de?nition r/w 2 bytes 0001h: m=0; n=1 de?nes the used gop structure as (n.m), where n is the number of frames per gop and m is the distance of 2 sequential i- or p-frames (reference frame distance); distance = 0 is i-frame coding; see table 3 for meaningful combinations. byte 0 distance (m) (0 to 3) byte 1 length (n) (0 to 19) 73 i, e, p, s user data gop header r/w 64 bytes all 0 speci?es the data to be inserted into the gop header. 74 i, e, p, s number of user data gop r/w 1 byte 0 speci?es the amount of user data to be inserted into the gop header. 75 i, e, p, s number of user data picture header r/w 1 byte 0 speci?es the amount of user data to be inserted into the picture header. 76 i, e, p, s user data picture header r/w 64 bytes all 0 speci?es the data to be inserted into the picture header. if internal user data insertion of closed caption data into the gop header is active and the gop size is larger than 9, then the insertion of user data to the picture header is not available. 77 i, e, p, s noise ?lter coef?cients r/w 2 bytes off de?nes the noise ?lter coef?cients gain and criterion scale. byte 0 gain byte 1 criterion 78 i adaptive quantization depth r/w 1 byte 0 to 128 32 selects the depth of quantization adaptation; 0 for no adaptation, 128 for maximum adaptation.
2004 jan 26 49 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. if no q matrix is downloaded then the default is the mpeg standard and no q matrix is inserted into the stream. 79 i quantizer matrix r/w 2 64 bytes array of integers (8 8 bytes) - speci?es the quantizer matrix as 2 tables, each an 8 8 array. data must be transferred column by column, not row by row. the inter q matrix must be downloaded ?rst, the intra q matrix downloaded second; note 1. 7a i reserved -- - - - 7b i disable forced backward prediction r/w 1 byte 0 applies only for gop structures starting with a b-frame: disabled forced backward prediction results in non-editable (open) gops with prediction from a former gop. enabled forced backward prediction results in backward predicted closed gops without prediction from a former gop. in all cases the leading b-frames of the very ?rst gop structure after start of encoding are forced to backward prediction. bit 0 = 0 enabled bit 0 = 1 disabled 7c i scan select r/w 1 byte 0 bit 0 = 0 alternate scan bit 0 = 1 zigzag scan 7d i quantizer scale table r/w 1 byte 0 bit 0 = 0 logarithmic bit 0 = 1 linear adr hex m command name r/w size/position parameter/range default description
2004 jan 26 50 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 21 i 2 c-bus video encoder: bit rate control (dynamic settings) note 1. if the video bit rate rmax is intended to be changed during the encoding state, the maximum applied value for rmax has to be set before start of encoding. i.e. the rmax value that was valid at start of encoding (coming from stop) is the maximum allowed value for this enco ding process. adr hex m command name r/w size/position parameter/range default description 80 i, e, p, s rvbr r/w 2 bytes - 6000 vbr target bit rate (kbit/s); this applies to vbr mode only; rvbr must be set to less than rmax. 81 i, e, p, s rmax r/w 2 bytes - 9800 cbr mode: target bit rate (kbit/s); vbr mode: maximum bit rate (kbit/s); note 1. 82 i, e, p, s qmin_vbr r/w 1 byte 1 to 112 4 minimum q-scale for external constraints of vbr 83 i, e, p, s qmax_vbr r/w 1 byte 1 to 112 12 maximum q-scale for external constraints of vbr. 84 i, e, p, s b-frame weighting r/w 1 byte 32 to 128 128, no weighting b-frame weighting factor (internally divided by 128; i.e. 128 = no effect) 85 i, e, p, s read bytes per gop r 4 bytes -- this command reads the number of bytes per gop.
2004 jan 26 51 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 22 i 2 c-bus audio encoder: bit rate control (static settings) adr hex m command name r/w size/position parameter/range default description 90 i disable audio encoder r/w 1 byte 0 speci?es if the audio encoder is enabled. if the audio encoder is disabled, no audio data will be inserted in the output stream. bit 0 = 0 enabled bit 0 = 1 disabled 91 i audio input format r/w 1 byte i 2 s de?nes the audio input format bit[2:0] = 000 i 2 s bit[2:0] = 001 reserved bit[2:0] = 010 eiaj 16 bits bit[2:0] = 011 eiaj 18 bits bit[2:0] = 100 eiaj 20 bits bit[2:0] = 101 eiaj alternative format 16 bits bit[2:0] = 110 eiaj alternative format 18 bits bit[2:0] = 111 eiaj alternative format 20 bits 92 i audio input mode and port select r/w 1 byte slave, port 1 in master mode, saa6752hs delivers the bit clock and word select signal. in slave mode, saa6752hs receives the bit clock and word select signal. remark: if i 2 s port 2 is switched to output mode (ves + aes output stream mode) then saa6752hs is ?xed to master mode. bit 0 = 0 master mode bit 0 = 1 slave mode bit 1 = 0 port 1 bit 1 = 1 port 2 93 i audio processing mode r/w 1 byte mpeg-1 l2 de?nes the audio processing mode (see section 7.5); note 1 bit[1:0] = 00 mpeg-1 l2 encode bit[1:0] = 01 ddc encode (only for saa6752hs/v103) bit[1:0] = 10 lpcm bypass bit[1:0] = 11 dvd bypass
2004 jan 26 52 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... notes 1. in systems that use 16 mbit sdram, due to system architecture constraints, lpcm bypass must be restricted to be used with i an d ip video encoding only. there is no constraint if 64 mbit sdram is used. 2. all compressed audio data is 16-bit. in the event of lpcm bypass 20-bit data will be truncated to 16 bits. 94 i audio encoding bit rate and output resolution r/w 1 byte 256 kbit/s 16-bit de?nes the audio encoding bit rate (see section 7.5); note 2 bit 0 = 0 256 kbit/s bit 0 = 1 384 kbit/s bit 1 = 0 16-bit bit 1 = 1 reserved 95 i audio clock output frequency r/w 1 byte 256 48 khz selects the output frequency at the audio clock mode bit 0 = 0 256 48 khz bit 0 = 1 384 48 khz 96 i audio pre-emphasis mode r/w 1 byte off selects audio pre-emphasis mode of input signal (valid for mpeg encoding only) bit[1:0] = 00 off bit[1:0] = 01 50/15 ms bit[1:0] = 10 ccitt j17 adr hex m command name r/w size/position parameter/range default description
2004 jan 26 53 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 23 i 2 c-bus audio encoder: bit rate control (dynamic settings) adr hex m command name r/w size/position parameter/range default description a0 e, p, s preamble pc r 1 byte i 2 s preamble pc in case of iec 61937 input (data type), applies to dvd bypass mode only bit[4:0] data type bit[6:5] reserved bit 7 error ?ag indicating validity of burst load a1 e, p, s preamble pd r 2 bytes preamble pd (16 bits) - preamble pd in case of iec 61937 input (payload length); this applies to dvd bypass mode only a2 e, p, s audio bit stream information r 8 bytes bit stream information (4 16 bits) - part of audio frame header in case of iec 61937 input; this applies to dvd bypass mode only. a3 - reserved -- - - - a4 all audio mute on/off r/w 1 byte 0 bit 0 = 0 off bit0=1 on
2004 jan 26 54 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 24 i 2 c-bus multiplexer: general (static settings) adr hex m command name r/w size/position parameter/range default description b0 i output stream format r/w 1 byte ps (dvd) selects the mpeg-2 output format (see saa6752hs output stream formats for details): bit[2:0] = 000 es video (ves) elementary stream (es): elementary stream output is possible for audio or video only encoding. bit[2:0] = 001 es audio (aes) bit[2:0] = 010 pes (dvd) packetized elementary stream (pes): dvd-compliant: pes packets have a limited size and can be easily multiplexed into a dvd program stream. ts-compliant: pes packets have an unlimited size and can be easily multiplexed into a transport stream. pes packets containing audio and video information are ?agged with an audio/video signal pin. the audio/video polarity of the signal pin is programmable. bit[2:0] = 011 pes (ts) bit[2:0] = 100 ps (dvd) program stream (ps): a dvd-compliant program stream is generated, but no navigation packs are inserted. bit[2:0] = 101 ts transport stream (ts): a transport stream is generated. bit[2:0] = 110 pack stream pack stream is a special not mpeg-compliant mode. the mpeg buffer model is not used. bit[2:0] = 111 ves + aes ves + aes mode allows ves output from the output port at the same time as an spdif formatted aes is output from the 2nd i 2 s audio port. for this mode subaddress 92h must be set to zero. b1 i maximum system bit rate r/w 2 bytes <27000; note 1 10080 maximum target bit rate of the system stream in kbit/s (= 1000 bit/s) and must be set if ts or ps or pack stream modes are selected. it is ignored if es or pes streams are selected. b2 i number of ?ushing bytes r/w 2 bytes - 0 number of ?ushing bytes appended to the stream after a stop.
2004 jan 26 55 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... b3 i video pes id r/w 8 bits e0h to efh e0h stream id for video pes header; must be set for ts, ps and pes output. b4 i audio pes id r/w 8 bits c0h to dfh c0h stream id for audio pes header; must be set for ts, ps and pes output. b5 i pes original copy and copyright r/w 1 byte copy, no copyright copy and copyright setting in audio and video pes header. bit0=1 or iginal bit0=0 copy bit1=1 copyr ight bit1=0 no copyr ight b6 i multiplexer special dvd ps settings r/w 1 byte 2 gops, off, metabyte, 0 (nav packet), inserted (pes header) bit[3:0] 1 to 15, number of gop/vobu the number of gops per vobu for ps output. bit4=0 metabyte output off enables/disables the output of metabytes for ps (dvd) and pack stream modes. bit4=1 metabyte output on bit[6:5] 0 to 3, time slot reservation for nav packets speci?es the number of reserved time slots for navigation packets and dvd recorder data. bit7=0 inserted determines if the pes header extension is inserted into the stream; this applies to program stream and pack stream modes. remark: for dvd-compliance, the pes header extension must be inserted. bit7=1 not inserted b7 i audio substream id r/w 1 byte - 00 audio substream id; for ps (dvd) or pes (dvd) only b8 e current system bit rate r 2 bytes -- current system bit rate of the system stream in kbit/s (= 1000 bit/s); applies for ps and ts modes. the parameter includes the number of stuf?ng bytes. during pause mode, this address will read back the value of the last gop before the pause command. b9 i enable mpeg end code r/w 1 byte disable enables the mpeg end code (for program stream only). bit0=1 enable bit0=0 disable adr hex m command name r/w size/position parameter/range default description
2004 jan 26 56 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. the limit for i-frame only is 27 mbit/s. for ip or ipb formats the limit is 16 mbit/s. table 25 i 2 c-bus multiplexer: transport stream (static settings) adr hex m command name r/w size/position parameter/range default description c0 i video ts packet id r/w 2 bytes 0020h to 1ffeh 0100h packet id for transport stream packets containing video data; for ts only. c1 i audio ts packet id r/w 2 bytes 0020h to 1ffeh 0102h packet id for transport stream packets containing audio data; for ts only. c2 i system information tables w 189 bytes (maximum value); up to 5 separate tables ?rst byte is table number range (0 to 4) + array of maximum 188 bytes values - there are 5 different tables followed by an array of up to 188 bytes.the tables must be sent one by one; the size of the tables is not de?ned but limited to 188 bytes. table 0: program association table (pat) table 1: program map table (pmt) table 2: free programmable [e.g. conditional access table (cat)] table 3: free programmable [e.g. network information table (nit)] table 4: free programmable [e.g. selection information table (sit)] c3 i ts miscellaneous r/w 1 byte 00h a discontinuity information table is inserted at the beginning of the stream (after a stop of recording). bit0=0 dit insertion disabled bit0=1 dit insertion enabled bit1=0 constant ts bit rate at constant ts bit rate mode null packets are delivered at the multiplexer output to achieve the constant ts bit rate. bit1=1 variable ts bit rate at variable ts bit rate mode no null packets are inserted at the multiplexer output. this mode can be used in combination with variable video bit rate. c4 i clock ts packet id r/w 2 bytes 0020h to 1ffeh 0104h packet id for transport stream packets containing pcr values; for ts only.
2004 jan 26 57 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 26 i 2 c-bus output interface adr hex m command name r/w size/position parameter/range default description d0 i r/w 1 byte de?nes the output interface in one byte (collects all sub parameter bits in one byte). all states de?ned are the active states output protocol bit[1:0] = 00 dio slave mode dio slave mode dio master mode: saa6752hs delivers the clock signal. dio slave mode: saa6752hs receives the clock signal. bit[1:0] = 01 dio master mode bit[1:0] = 10 not applicable bit[1:0] = 11 debi slave mode data valid pin polarity bit 2 = 0 positive positive for the debi output protocol negative polarity has to be selected bit 2 = 1 negative high-impedance on/off bit 3 = 0 off on selection of high-impedance for output pin. bit3=1 on audio/video pin polarity bit 4 = 0 audio high, video low audio high, video low bit 4 = 1 audio low, video high sync pin polarity bit 5 = 0 positive positive bit 5 = 1 negative data request pin polarity bit 6 = 0 negative negative bit 6 = 1 positive pdo clock frequency bit 7 = 0 9 mhz 9 mhz selection of clock frequency for dio master mode bit 7 = 1 6.75 mhz f6 i insert leading null bytes w 2 bytes number of bytes 00h de?nes the number of leading null bytes (00h), which are delivered to the output before the start of the stream. remark: after forced recon?gure command the default value of 00h will be set.
2004 jan 26 58 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 10 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. all pads are not 5 v tolerant. 2. pins xtali and xtalo. 3. at v ddp > 3.7 v only maximum 4.2 v at digital outputs is allowed. 4. short-circuit current is only allowed for a short time (<1 s). 5. human body model: c = 100 pf; r = 1.5 k w . 6. machine model: c = 200 pf; l = 0.75 m h; r = 0 w . 11 thermal characteristics symbol parameter conditions min. max. unit v ddp digital supply voltage for pads - 0.5 +4.0 v v ddco digital supply voltage for core - 0.5 +2.8 v v dda analog supply voltage - 0.5 +2.8 v v i digital input voltage note 1 - 0.5 +4.0 v v i analog input voltage note 2 - 0.5 +2.8 v v o digital output voltage note 3 - 0.5 v ddp + 0.5 v i sc short-circuit current of output pads note 4 - 125 ma i lu(prot) latch-up protection current - 100 ma p tot total power dissipation - 2w t stg storage temperature - 25 +125 c t amb ambient temperature 0 70 c v es electrostatic handling voltage note 5 - 2000 +2000 v note 6 - 150 +150 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air; soldered to a pcb with supply and ground plane 28 k/w
2004 jan 26 59 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 12 characteristics v ddco = 2.5 v, v dda = 2.5 v and v ddp = 3.3 v for the i/o pads; supply voltages v ddco and v dda are connected externally together; grounds v ssco , v ssa and v ssp are connected externally together; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies: pins v ddp , v ddco and v dda v ddp digital supply voltage (pad cells) 3.0 3.3 3.6 v v ddco digital supply voltage (core) 2.3 2.5 2.7 v v dda analog supply voltage (oscillator and pll) 2.3 2.5 2.7 v i ddp digital supply current (pad cells) 17 25 37 ma i ddco digital supply current (core) 390 430 500 ma i dda analog supply current - 3 - ma p tot total power dissipation 0.95 1.16 1.48 w input: pins yuv0 to yuv7 v il low-level input voltage - 0.5 - +0.7 v v ih high-level input voltage 1.7 - v ddp v v hys hysteresis voltage 0.4 -- v i il low-level input current v il =v ssp - 5 -- m a i ih high-level input current v ih =v ddp -- 5 m a c i input capacitance -- 10 pf input with pull-up resistor: pins cts, extclk, i2caddrsel, pdids, reset, rxd, tck, tdi, tms and trst v il low-level input voltage - 0.5 - +0.7 v v ih high-level input voltage 1.7 - v ddp v v hys hysteresis voltage 0.4 -- v i pu(l) low-level pull-up input current v il =v ssp - 20 - 50 - 70 m a i pu(h) high-level pull-up input current v ddco 2004 jan 26 60 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs inputs/outputs with i max = 4 ma: pins pdioclk, sm_cs0, sm_lb, sm_ub, test0, test1 and test2 v il low-level input voltage - 0.5 - +0.7 v v ih high-level input voltage 1.7 - v ddp v v hys hysteresis voltage 0.4 -- v v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddp - 0.4 - v ddp v i sc short-circuit current note 1 - 55 - +55 ma i tl 3-state leakage current v ih =v ddp ; v il =v ssp - 5 - +5 m a c i input capacitance -- 10 pf c l load capacitance -- 30 pf inputs/outputs with i max = 4 ma and pull-down resistor: pins sclk1, sclk2, sdata2, sm_d0 to sm_d15, sws1 and sws2; note 2 v il low-level input voltage - 0.5 - +0.7 v v ih high-level input voltage 1.7 - v ddp v v hys hysteresis voltage 0.4 -- v v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddp - 0.4 - v ddp v i sc short-circuit current note 1 - 55 - +55 ma i pd pull-down input current v ddco 2004 jan 26 61 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 3-state output with i max = 4 ma: pins pdo0 to pdo7, pdoav and pdosync; note 2 v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddp - 0.4 - v ddp v i sc short-circuit current note 1 - 55 - +55 ma i tl 3-state leakage current v ih =v ddp ; v il =v ssp - 1 - +1 m a c l load capacitance -- 30 pf 3-state output with i max = 4 ma and pull-up resistor: pin pdoval; note 2 v ol low-level output voltage i ol =4ma -- 0.4 v v oh high-level output voltage i oh = - 4ma v ddp - 0.4 - v ddp v i sc short-circuit current note 1 - 55 - +55 v i pu(l) low-level pull-up input current v il =v ssp - 20 - 50 - 70 m a i pu(h) high-level pull-up input current v ddco 2004 jan 26 62 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs v ol low-level output voltage; open-drain 3 ma sink current 0 - 0.4 v t low scl low time 1.3 -- m s t high scl high time 0.6 -- m s t r(i2c) rise time of both sda and scl -- 0.3 m s t f(i2c) fall time of both sda and scl -- 0.3 m s t su;dat data set-up time 100 -- ns t hd;sta hold time start condition 0.6 -- m s t su;sto set-up time stop condition 0.6 -- m s video clock input timing: pins vclk1 and vclk2; see fig.15 t cy cycle time 35 37 39 ns d duty factor t high /t cy 40 50 60 % t r(vclk) rise time v i = 0.8 to 2 v -- 5ns t f(vclk) fall time v i = 2 to 0.8 v -- 6ns video input data and control timing: pins yuv7 to yuv0, fid, hsync and vsync; see fig.15 t su;dat data set-up time 6 -- ns t hd;dat data hold time 3 -- ns video input parameter range f i(d) data input frequency rate frame-locked; notes 5 and 6 25.46 27 28.54 mhz f h line frequency 625 lines; note 6 14734 15625 16515 khz 525 lines; note 6 14837 15734 16631 khz f v ?eld frequency 625 lines; notes 7 and 8 46 50 50.75 khz 525 lines; notes 7 and 8 55 60 60.9 khz n al/f active lines/?eld 625 lines; notes 7 and 9 265 288 311 525 lines; notes 7 and 9 221 240 259 crystal oscillator: pins xtali and xtalo; note 10 f xtal fundamental frequency note 11 27 (1 - 80 10 - 6 ) 27 27 (1+80 10 - 6 ) mhz f stab mpeg2 frequency stability note 11 27 (1 - 30 10 - 6 ) - 27 (1+30 10 - 6 ) mhz c l load capacitance 8 10 12 pf v il low-level input voltage if used with external clock - 0.5 - +0.7 v symbol parameter conditions min. typ. max. unit
2004 jan 26 63 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs v ih high-level input voltage if used with external clock 1.7 - v dda v c shunt shunt capacitance -- 7pf r s serial resistance -- 25 w crystal oscillator tuning: pins xtali and xtalo; note 10 n tune tuning steps - 127 - +128 c tune(min) minimum internal tuning capacitance to v ssa n tune = 128 - 8 - pf c tune(max) maximum internal tuning capacitance n tune = - 127 - 72 - pf f step crystal frequency offset per tuning step 14 42 70 hz external clock input: pin extclk f extclk external frequency square wave; note 11 25.7 27.0 28.3 mhz d duty factor t high /t cy 40 50 60 % t r(extclk) rise time v i = 0.7 to 1.7 v -- 5ns t f(extclk) fall time v i = 1.7 to 0.7 v -- 6ns i 2 c-bus address select input: pin i2caddrsel v il low-level input voltage for i 2 c-bus addresses 40h and 41h - 0.5 - +0.7 v v ih high-level input voltage for i 2 c-bus addresses 42h and 43h 1.7 - v ddp v reset input: pin reset v il low-level input voltage for active reset - 0.5 - +0.7 v t start start time of ?rst reset pulse after power-on - 010 m s t length length of reset pulse after power-on and after sleep 10 -- ms t init initialization phase after reset pulse until i 2 c-bus commands are accepted -- 1s symbol parameter conditions min. typ. max. unit
2004 jan 26 64 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs sdram interface data, address and control timing: pins sd_dq31 to sd_dq0, sd_a13 to sd_a0, sd_cas, sd_ras, sd_we and sd_oe t cy cycle time f sys = 27 mhz - 9.26 - ns t cas cas latency time - 3 - clock cycles t rcd row to column delay time - 3t cy - ns t rrd activate to activate delay time - 2t cy - ns t rp row precharge time - 3t cy - ns t wr write recovery time - 2t cy - ns t rsc mode register set cycle time - 2t cy - ns t ras row activate time - 6t cy - ns t rc row cycle time - 8t cy - ns t power-up wait time after power-on 500 515 -m s t d(c-d) clock to data output delay c l(sd_clk) = 15 pf; c l(sd_dqn) = 8 pf; f sd_clk = 108 mhz 2.5 4.0 5.0 ns t d(c-a) clock to address output delay c l(sd_clk) = 15 pf; c l(sd_an) = 8 pf; f sd_clk = 108 mhz 2.5 4.0 5.0 ns t su(d) data input set-up time 1 -- ns t h(d) data input hold time 2.5 -- ns data output interface timing: pins pdo7 to pdo0, pdids, pdosync, pdoav and pdioclk t l-o(pdids-pdoval) pdids to pdoval low-ohmic time debi slave mode 0 - 20 ns t l-o(pdids-pdo) pdids to pdo[7:0] low-ohmic time debi slave mode 0 - 20 ns t stab(pdo-pdoval) pdo[7:0] data stable to falling pdoval time debi slave mode 10 -- ns t r(pdoval-pdo) rising pdoval to pdo[7:0] high-impedance time debi slave mode 10 -- ns t h(pdo-pdioclk) pdo[7:0] data to pdioclk hold time dio master mode; pdoval = 1 10 -- ns t su(pdo-pdioclk) pdo[7:0] data to pdioclk set-up time dio master mode; pdoval = 1 10 -- ns t i(pdioclk)h input pdioclk high time dio slave mode 55 -- ns t i(pdioclk)l input pdioclk low time dio slave mode 55 -- ns t stab(pdioclk-pdo) falling input pdioclk to pdo[7:0] data stable time dio slave mode; pdoval = 1 36 - 58 ns symbol parameter conditions min. typ. max. unit
2004 jan 26 65 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs notes 1. short-circuit current is only allowed for a short time (<1 s). 2. the output pins are 3.3 v tolerant when in 3-state mode. 3. pins scl and sda of the i 2 c-bus interface do not obstruct the sda and scl lines if the supply voltage v ddp is switched off. 4. the open-drain outputs are 3.3 v tolerant. 5. frame-locked input data rate deviation from saa6752hs crystal clock. 6. supporting output range of the philips saa7114 video input processor. 7. applies for line frequencies 2% from nominal. 8. minimum limit according to iec 60756; maximum limit because the saa6752hs may drop frames for v-sync frequencies greater than 1.5% above nominal. 9. deviation according to iec 60756.7. the saa6752hs will only encode 240 lines (when in 525-line mode) and 288 lines (when in 625-line mode). therefore any additional lines in a field above these values will not be encoded. 10. pin xtalo has to be used for connection with a crystal only. do not use for other purposes. 11. the required stability of the crystal frequency or external system clock is dependent upon the clock mode used in the application. handbook, full pagewidth mhc142 valid not valid valid 1.7 v 0.7 v 1.7 v 1.3 v 0.7 v data and control inputs vclk t cy t low t high valid not valid valid 2.4 v 0.4 v data and control outputs t f(vclk) t hd;dat t r(vclk) t su;dat t oh;dat fig.15 clock data timing.
2004 jan 26 66 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 13 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.50 0.25 3.6 3.2 0.25 0.27 0.17 0.20 0.09 28.1 27.9 0.5 30.9 30.3 1.39 1.11 8 0 o o 0.08 0.2 1.3 0.08 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot316-1 ms-029 00-01-25 03-02-25 d (1) (1) (1) 28.1 27.9 h d 30.9 30.3 e z 1.39 1.11 d pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 52 c d h b p e h a 2 v m b d z d a z e e v m a x 1 208 157 156 105 104 53 y w m w m 0 5 10 mm scale 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height sqfp208: plastic shrink quad flat package; sot316-1 a max. 4.1
2004 jan 26 67 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 14 soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 14.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson-t and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2004 jan 26 68 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 14.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2004 jan 26 69 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs 15 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 16 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 jan 26 70 philips semiconductors product speci?cation mpeg-2 video and mpeg-audio/ac-3 audio encoder with multiplexer saa6752hs ics with mpeg-audio/ac-3 audio functionality ? purchase of a philips ic with an mpeg-audio and/or ac-3 audio functionality does not convey an implied license under any patent right to use this ic in any mpeg-audio or ac-3 audio application. a license can be obtained via philips intellectual property & standards (internet at url http://www.ip.philips.com; e-mail info.licensing@philips.com). ics with mpeg-2 functionality ? use of this product in any manner that complies with the mpeg-2 standard is expressly prohibited without a license under applicable patents in the mpeg-2 patent portfolio, which license is available from mpeg la, l.l.c., 250 steele street, suite 300, denver, colorado 80206. 18 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r04/03/pp 71 date of release: 2004 jan 26 document order number: 9397 750 12538

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